Abstract: A transfer-mold type power module includes a plurality of electrode terminals that is arranged so as to protrude in the same direction from a target side surface of a package. A tie bar cutting residue protruding from a first side surface of each of the electrode terminals and a tie bar cutting residue protruding from a second side surface of each of the electrode terminals are different in position in a length direction of each of the electrode terminals. Each of the electrode terminals has a shape bent at a position including tie bar cutting residue closer to the package, with a width direction of each of the electrode terminals as an axis.

Abstract: A semiconductor module includes a semiconductor device and bus bar. The device includes an insulating substrate, conductive member, switching elements, and first/second input terminals. The substrate has main/back surfaces opposite in a thickness direction, with the conductive member disposed on the main surface. The switching elements are connected to the conductive member. The first input terminal, including a first terminal portion, is connected to the conductive member. The second input terminal, including a second terminal portion overlapping with the first terminal portion in the thickness direction, is connected to the switching elements. The second input terminal is separate from the first input terminal and conductive member in the thickness direction. The bus bar includes first/second terminals. The second terminal, separate from the first terminal in the thickness direction, partially overlaps with the first terminal in the thickness direction.

Abstract: A semiconductor module includes: an insulating heat dissipation sheet; a semiconductor device provided on the heat dissipation sheet; a lead frame including a lead terminal and a die pad which are formed integrally; a wire connecting the lead frame to the semiconductor device and constituting a main current path; and a mold resin scaling the heat dissipation sheet, the semiconductor device, the lead frame and the wire, wherein the lead terminal is led out from the mold resin, the heat dissipation sheet is in direct contact with an undersurface of the die pad, and the wire is bonded to the die pad directly above a contact part provided between the die pad and the heat dissipation sheet.

Abstract: A display substrate, comprising a plurality of light emitting units of different colors, each of which comprises: an electron transport layer, a hole transport layer, a quantum-dot light emitting layer located between the electron transport layer and the hole transport layer; and a hydrophilicity and hydrophobicity variable layer, located between the electron transport layer and the quantum-dot light emitting layer and configured to undergo an exposure treatment to change hydrophilicity and hydrophobicity of sides of the hydrophilicity and hydrophobicity variable layer that are in contact with the electron transport layer and the quantum-dot light emitting layer.

Abstract: A stack of the embodiment includes: a first magnetic substance; a second magnetic substance; and a first nonmagnetic substance which is disposed between the first magnetic substance and the second magnetic substance and contains at least one first metal element (M1) selected from the group consisting of ruthenium (Ru) and osmium (Os) and at least one second metal element (M2) selected from the group consisting of rhodium (Rh) and iridium (Ir). A magnetic device of the embodiment includes: a third magnetic substance; the stack; and a second nonmagnetic substance which is disposed between the third magnetic substance and the stack.

Abstract: A sensor package structure is provided and includes a substrate, a sensor chip disposed on the substrate, a padding layer disposed on the substrate, a plurality of wires, a support, and a light-permeable layer disposed on the support. A top side of the padding layer is coplanar with a top surface of the sensor chip, the support is disposed on the top side of the padding layer and the top surface of the sensor chip, and the wires are embedded in the support. Terminals at one end of the wires are connected to the top surface of the sensor chip, and terminals at the other end of the wires are connected to the top side of the padding layer, so that the sensor chip can be electrically coupled to the substrate through the wires and the padding layer.

Abstract: A semiconductor structure includes a semiconductor fin disposed over a substrate, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, a silicide layer disposed over the epitaxial S/D feature, the silicide layer is disposed on sidewalls of the epitaxial S/D feature, a dielectric layer disposed over sidewalls of the silicide layer, and an S/D contact disposed over the epitaxial S/D feature in an interlayer dielectric (ILD) layer.

Abstract: A bottom pinned magnetic tunnel junction (MTJ) stack having improved switching performance is provided which can be used as a component/element of a spin-transfer torque magnetoresistive random access memory (STT MRAM) device. The improved switching performance which, in turn, can reduce write errors and improve write voltage distributions, is obtained by inserting at least one heavy metal-containing layer into the magnetic free layer and/or by forming a heavy metal-containing layer on a MTJ capping layer that is located above the magnetic free layer.

Abstract: A radar system for tracking UAVs and other low flying objects utilizing wireless networking equipment is provided. The system is implemented as a distributed low altitude radar system where transmitting antennas are coupled with the wireless networking equipment to radiate signals in a skyward direction. A receiving antenna or array receives signals radiated from the transmitting antenna, and in particular, signals or echoes reflected from the object in the skyward detection region. One or more processing components is electronically coupled with the wireless networking equipment and receiving antenna to receive and manipulate signal information to provide recognition of and track low flying objects and their movement within the coverage region. The system may provide detection of objects throughout a plurality of regions by networking regional nodes, and aggregating the information to detect and track UAVs and other low flying objects as they move within the detection regions.

Abstract: A multi-chip package includes a first die having temperature sensors and a second die. The first die generates temperature deviation information of m (m<n) bits based on temperature information of n bits produced by the temperature sensors. The first die provides the temperature deviation information of m bits rather than the temperature information of n bits to the second die. An internal operation of the second die is controlled using the temperature deviation information output by the first die.

Abstract: Provided is a semiconductor device which is a facedown mounting, chip-size-package-type semiconductor device and includes: a transistor element including a first electrode, a second electrode, and a control electrode which controls a conduction state between the first electrode and the second electrode; a plurality of first resistor elements each including a first electrode and a second electrode, the first electrodes of the first resistor elements being electrically connected to the second electrode of the transistor element; one or more external resistance terminals to which the second electrodes of the plurality of first resistor elements are physically connected; a first external terminal electrically connected to the first electrode of the transistor element; and an external control terminal electrically connected to the control electrode.

Abstract: The present disclosure generally relates to magnetoresistive device apparatus and methods. The magnetoresistive device includes a read head. The read head is a tunneling magnetoresistive reader that includes a multilayer free layer structure. The multilayer structure includes one or more layers of Co or FCC FeCo sandwiched between a BCC CoFe50 nanolayer and an amorphous CoFeB layer. The one or more layers of Co or FCC FeCo create nanocrystalline disorder that allows the thickness of the amorphous CoFeB layer to be reduced while retaining or even improving TMR and reducing the interlayer coupling field.

Abstract: Present disclosure provides a semiconductor structure, including a semiconductor substrate, an insulator fin over the semiconductor substrate, the insulator fin having a principle dimension, from a cross sectional perspective, perpendicular to a top surface of the semiconductor substrate, and a semiconductor capping layer cover the insulator fin along the principle dimension. A method for manufacturing a semiconductor structure is also disclosed in the present disclosure.

Abstract: A domain wall type magnetic recording element includes a first ferromagnetic layer containing a ferromagnetic material, a magnetic recording layer extending in a first direction which intersects a lamination direction of the first ferromagnetic layer and containing a magnetic domain wall, and a nonmagnetic layer sandwiched between the first ferromagnetic layer and the magnetic recording layer, in which the magnetic recording layer includes a recessed part or a protruding part, which is configured to trap the magnetic domain wall, on a side surface, and a width of the first ferromagnetic layer is smaller than a smallest width of the magnetic recording layer in a second direction perpendicular to the first direction in a plan view from the lamination direction.

Abstract: Data storage devices are provided. A data storage device includes a memory transistor on a substrate and a data storage structure electrically connected to the memory transistor. The data storage structure includes a magnetic tunnel junction pattern and a top electrode on the magnetic tunnel junction pattern. The top electrode includes a first top electrode and a second top electrode on the first top electrode, and the first and second top electrodes include the same metal nitride. The first top electrode includes first crystal grains of the metal nitride, and the second top electrode includes second crystal grains of the metal nitride. In a section of the top electrode, the number of the first crystal grains per a unit length is greater than the number of the second crystal grains per the unit length.

Abstract: A semiconductor device comprises a substrate including a cell array region and a peripheral circuit region that surrounds the cell array region. The cell array region includes landing pads disposed on the substrate and first bottom electrodes disposed on and connected to corresponding landing pads. The peripheral circuit region includes conductive lines disposed on the substrate, a first conductive pad disposed on and spaced apart from the conductive lines, a dielectric pattern disposed between the conductive lines and the first conductive pad, and a plurality of second bottom electrodes disposed on and connected in common to the first conductive pad. A height of each of the first bottom electrodes is greater than a height of each of the second bottom electrodes. Top surfaces of the first bottom electrodes are located at a same level as a level of top surfaces of the second bottom electrodes.

Abstract: In a semiconductor module, two switching elements are connected in parallel to each other. Each of the switching elements includes a first main electrode formed on one surface side, and a second main electrode and a gate electrode formed on a rear surface side opposite to the one surface side. A first conductor plate is coupled with two first main terminals at first coupling portions and is electrically connected with the first main electrodes. A second conductor plate is coupled with one second main terminal at a second coupling portion and is electrically connected with the second main electrodes. The second coupling portion is disposed between the switching elements in an alignment direction of the switching elements, and the first coupling portions are provided on both sides of the second coupling portion in the alignment direction.

Abstract: A semiconductor die includes a semiconductor body having first and second active portions. The first active portion includes first source regions. The second active portion includes second source regions. A gate structure extends from a first surface into the semiconductor body and has a longitudinal gate extension along a lateral first direction. A first load pad and the first source regions are electrically connected. A second load pad and the second source regions are electrically connected. A gap laterally separates the first and second load pads. A lateral longitudinal extension of the gap is parallel to the first direction or deviates therefrom by not more than 60 degree. A connection structure electrically connects the first and second load pads. The connection structure is formed in a groove extending from the first surface into the semiconductor body and/or in a wiring layer formed on the first surface.

Abstract: Disclosed is a temporary protective film for semiconductor sealing molding comprising: a support film; and an adhesive layer provided on one surface or both surfaces of the support film and containing a resin and a silane coupling agent, and the content of the silane coupling agent in the temporary protective film may be more than 5% by mass and less than or equal to 35% by mass with respect to the total mass of the resin.

Abstract: A semiconductor package includes a substrate, an electronic component, a dielectric layer a transmitting antenna, a receiving antenna and a FSS (Frequency selective surface) antenna. The electronic component is disposed on and electrically connected with the substrate. The dielectric layer has a dielectric upper surface. The transmitting antenna and the receiving antenna are formed adjacent to the substrate. The FSS antenna is formed adjacent to the dielectric upper surface of the dielectric layer. The FSS antenna is separated from the substrate by the dielectric layer in a wireless signal emitting direction.