Abstract: An enhancement filter for an oscilloscope is disclosed wherein the enhancement filter may be initially calibrated for one or more channels and/or for one or more attenuation settings such as 50 mV per division, 100 mV per division, and/or 200 mV per division, for example. In one embodiment, a desired filter response is selected to have a modified Gaussian type filter function having an at least approximately linear phase response, wherein the transfer function of the desired filter response comprises a step response that is be stored in the oscilloscope to be used as a part of calibration system of the oscilloscope.
Abstract: A method is provided for managing inspection requirements using a network-based system. The system includes a server system coupled to a centralized database and at least one client system. The method includes receiving information relating to a plurality of components of a specific plant and storing the information into a centralized database. The method further includes cross-referencing the information received, updating the centralized database based on the information received and providing information in response to an inquiry.
July 11, 2001
Date of Patent:
August 3, 2004
General Electric Company
Randal Raymond Stark, Sampath Ranganath, Ahdee Quan Chan
Abstract: A method and structure for measuring the minimum lock frequency of a delay locked loop (DLL) within a programmable integrated circuit device such as a field programmable gate array (FPGA). The device is temporarily configured such that one DLL is programmed as a ring oscillator (RO) and connected directly to the input terminal of a second DLL (the DLL under test). Optionally, the RO is connected to the DLL under test through a divider to provide a lower DLL drive frequency. To test the DLL, the RO frequency is decreased until the DLL under test fails to lock. The frequency of the RO at that point is measured by comparing its output signal to the known frequency of an external clock source using two counters, and decremented until the DLL locks successfully. The lock frequency of the DLL under test is then computed from the ratio of the counter values.
Abstract: Highly accurate time interval measurement is achieved for an electrical waveform. The electrical waveform is sampled and converted to a series of voltages, and the series of voltages is interpolated in order to form a time tag list, using interpolations that are optimized for time interval measurement and analysis. The time tag list accurately represents the times at which particular events of interest occur, and is used to generate displays and results analysis such as adjacent cycle jitter and accurate differential triggering and analysis.
Abstract: A computer system includes a compression engine for compressing a decompressed sequence of data to produce a compressed sequence of data. The compression engine encodes each piece of data in the decompressed sequence of data as either a portion of a copy token or as a literal token. Tokens are grouped together into groups of up to 8 tokens and a bitmap holding 8 bits is provided to identify the respective tokens as either copy tokens or literal tokens. The copy tokens encode sub-sequences of data that have previously occurred in the decompressed data sequence. Each copy token is of a like size but includes a variable-sized offset field for encoding an offset between a current occurrence of a sub-sequence of data and a previous occurrence of a sub-sequence of data. The offset field is variable-sized to encode the offset in a minimal number of bits. The computer system also includes a decompression engine for decompressing data sequences that have been compressed using the compression engine.
Abstract: For transmission and reception of an ADPCM stream in which each of signal components is represented by a predetermined number of bits, an ADPCM transcoder comprises a bit number determining device (43) for producing a bit number signal representative of first and second bit numbers one at a time to make the ADPCM stream carry a voice component with the first bit number and a data component with the second bit number as two of the signal components. The first bit number is less than the second bit number. Preferably, a sum of the first and the second bit numbers is not greater than twice the predetermined number to make one of the two signal components comprise the voice component and a less significant part of the data component. The first and the second bit numbers are calculated from a voice and a data optimum scale factor which can be calculated by a method similar to adaptive prediction. The bit number signal need not be carried by the ADPCM stream.
Abstract: A digitizer comprising a microprocessor, a quartz oscillator, a cursor or stylus, an overlapped loop assembly, a peak phase recognizer, an analog/digit converter and other matching devices including multiplexers, amplifiers, filters and etc., wherein the overlapped loop assembly includes a plurality of loops for horizontal axis respectively starting from the left and the middle and a plurality of loops for vertical axis respectively starting from the bottom and the middle to overlap on the loops for horizontal axis forming into an induction area, the first loop for the horizontal axis at the left being connected to the first loop for the horizontal axis at the middle and the posterior loops for the horizontal axis at the left as well as the loops for the vertical axis at the bottom being respectively connected to the posterior loops for the horizontal axis at the middle and the loops for the vertical axis at the middle.
Abstract: A digital-to-analog converter has a plurality of switches, each of which being responsive to a bit of a digital signal having n bits, to selectively pass therethrough a weighted current having a magnitude of 2.sup.i-1 Ic where i is an ith bit. The respective weighted current flows through a corresponding transistor into a resistor ladder circuit. The resistor ladder circuit has a plurality of arms, each of which receive a weighted current from the emitter of a corresponding transistor. The digital-to-analog converter further includes a plurality of base resistors connected in series such that the bases of the transistors are connected with corresponding junctions of the base resistors r1-r7. The plurality of base resistors carry a first current therethrough.
Abstract: A timing control for precharged digital circuits to avoid spurious error appearing at the output due to the slow pull-down of the precharged node after precharging. A NAND gate is used to delay the precharged node siganl transmitting to the output stage until the precharged node is fully discharged. This timing control circuit is used to prevent any spurious peaking of the output of an analog-to-digital converter using precharged bit lines.
November 29, 1991
Date of Patent:
June 29, 1993
Industrial Technology Research Institute
Abstract: A D/A converter includes a D/A conversion part for converting a digital input signal into an analog output signal, a parameter setting part for generating a plurality of circuit parameters which define a voltage range of the analog output signal, and a setting control part for selecting desired circuit parameters from the plurality of circuit parameters in accordance with data supplied from an external device, so that the D/A conversion part generates the analog output signal having a voltage based on the desired circuit parameters.
Abstract: An A/D converter comprising a plurality of inputs, an input selection array to select one of the input signals, an A/D circuit providing a digital output and a conversion completion signal, a counter for sweeping a contiguous subset of the input channels sequentially, the counter incrementing once each time the conversion completion signal is asserted and resetting to point to the first channel in the subset after reaching the last channel in the subset, a channel memory for storing the value of the counter while an optional channel is selected for conversion without regard to the present position of the sweeping counter, a return bus, activated by the conversion completion signal, for replacing the value of the counter after the optional conversion is complete and returning to the normal sweep sequence in the previous position in the sequence, thereby avoiding useless conversion operations.
Abstract: A delta modulator automatically adjusting the slewing rate is disclosed. In the absence of a transition in the output data of a delta modulator, the current used for the integrator of the delta modulator is increased. When the comparator of the modulator indicates that the feedback signal of the modulator has overshot the input signal, the current is decreased or reversed until the two signals are approximately equal as signalled by a 50% duty cycle.
August 21, 1991
Date of Patent:
May 4, 1993
Melvyn Engel, Michael A. Sowell, Michael D. Bethel
Abstract: An automatically gain controlled multiple approximation analog to digital converter including a gain controlled amplifier responsive to the difference between an analog input signal and an analog version of a digital approximation of the analog input signal for providing a gain controlled analog residue signal, a quantizer for converting the gain controlled analog residue signal to a gain controlled digital residue signal, a digital divide circuit for dividing the gain controlled digital residue signal by a factor representative of the gain contained therein to provide a restored digital residue signal representative of the analog residue signal before it was amplified by the gain controlled amplifier, and a summing circuit for adding the restored digital residue signal and the digital approximation to provide the output of the gain controlled analog to digital converter.
Abstract: A format converter for converting an input signal having a specified format to a digital signal of a pre-existing format, and for converting the digital signal back to the input signal automatically, loads an active data portion of the input signal into an input first-in/first-out (FIFO) buffer at a first data rate and reads the active data portion together with dummy filler samples from the FIFO at a second data rate as the digital signal. The number, location and/or values of the filler samples identify the specified format. In reverse the filler samples are stripped from the digital signal and the resulting active samples are loaded into an output FIFO at the second data rate. The stripped filler samples are used to determine the specified format of the original source of the data signal, and the active samples are read from the output FIFO at the first data rate in the specified format to reproduce the input signal.
Abstract: Sigma-delta converter for converting an analog input signal into a sigma-delta code. The converter includes a threshold device (222) for generating an output and feedback signal, a filter receiving said analog input signal and said feedback signal from at least one feedback loop. The sigma-delta converter further includes circuits (221, 222) located in said feedback loop for performing a return-to-zero of the sigma-delta code generated by said threshold device at every period of the sigma delta clock, whereby said sigma-delta converter is insensitive to the asymmetry of the rise and fall time of the threshold device. This results in an increase of the signal-to-noise ratio and linearity of the converter, allowing the manufacture of a sigma-delta convertor with discrete components without requiring the development of an integrated circuit using switched capacitor technology.
Abstract: An improved dual slope integrating analog-to-digital converter for use in a Digital Multi-Meter includes an input portion, an A/D core portion, and a digital portion. The A/D core portion includes an auto zero function capability for automatically compensating for any existing offset voltages in various measurement modes such as voltage, resistance, or current measurement modes. The improved A/D converter of the present invention operates at high speed and with high resolution.
Abstract: An digital-to-analog converting circuit comprises a reference voltage generating circuit for generating a plurality of different reference voltages, and a reference voltage selection circuit receiving the plurality of reference voltages for supplying two adjacent reference voltages selected in accordance with the most significant portion of a digital signal which should be converted into an analog signal. A digital-to-analog converter receives the two selected reference voltages as the highest level reference voltage and the lowest level reference voltage of the digital-to-analog converter. This digital-to-analog converter is controlled by the remaining portion of the digital signal so as to supply an analog voltage which is obtained by dividing a voltage range from one to the other of the two selected reference voltages into a plurality of voltage levels and by selecting one from the plurality of voltage levels in accordance with the remaining portion of the digital signal.
Abstract: A digital data transmission system wherein binary coded data to be transmitted over the system is converted into a five-level (penternary or quinternary) line code prior to transmission over the system and is reconverted to binary data after transmission over the system. The choice of penternary word is conditional on the previous penternary word.
Abstract: Analog-to-digital converter operating in parallel having an analog signal input and a number of digital signal outputs, comprising a plurality of comparators having each two inputs and one output, one input being connected to an impedance network for supplying this one input with its own predetermined reference voltage, and the second input being connected to the analog signal input for receiving an analog input signal to be converted, so that each of the comparators processes a predetermined input signal portion. The comparator outputs are coupled to corresponding digital signal outputs, while delay elements are inserted between the comparator outputs and the corresponding digital signal outputs for causing a delay to occur related to the steepness of the slope of the input signal portion of the relevant comparator.
November 6, 1991
Date of Patent:
February 23, 1993
U.S. Philips Corporation
Rudy J. van de Plassche, Petrus G. M. Baltus
Abstract: A microcontroller based analog-to-digital converter is disclosed. The microcontroller is coupled to an output of a comparator. The comparator includes an input for receiving an unknown analog voltage and an input coupled to a capacitor. The capacitor is also coupled to the microcontroller through a resistor. Based upon the output of the comparator, the microcontroller provides a pulsed input signal with a predetermined duty cycle to the capacitor. The duty cycles for "high" pulses and "low" pulses are individually set to match a selected input voltage range. The rate at which pulses are applied to the capacitor is adjusted until the voltage on the capacitor matches the input voltage being measured. The pulsed input signal is monitored to establish a pulse count. Based upon the pulse count, the unknown analog voltage value is converted to a corresponding digital voltage value.