Abstract: In a digital to analog converter of the type having an array of current sources that are selected according to a digital input code to produce a current sum that is an analog of the digital code, current sources are arranged in pairs to form a dual current cell. When a dual current cell is selected, it produces two currents of differing magnitudes that are summed on two output busses with corresponding currents from other selected dual cells. These currents are subtracted to form an analog current. The two currents tend to have similar errors from a nominal current value and these errors are canceled by the subtraction. The two current sources of each dual current cell are oppositely switchable between two current levels, and the number of current sources is the minimum number commonly used for arrays of current cells having only one current source.

Abstract: A parallel type analog to digital (A/D) converter in which an input signal and reference voltages are differentially amplified by differential converting circuits, interpolation resistors are inserted between the outputs and between the complementary outputs of the differential converting circuits, and a tap voltage between the interpolation resistors is A/D converted, so that the A/D converter can operate at a high accuracy and at a high speed.

Abstract: A class of optimal nonlinear decoding algorithms for data acquisition applications of Sigma Delta modulators is applicable to all current Sigma Delta structures, including single and double loop, cascade and interpolative modulators. The decoding method takes on a particularly simple form for the case of constant modular inputs. While the performance of the present invention is identical to other optimal nonlinear decoding schemes such as table look-up, the present invention is simpler to implement. Numerical results show that the performance of the invention exceed that of conventional linear decoding.

Abstract: An apparatus for encoding variable bit length data words into constant bit length data words concatenates the variable length data words supplied at a first data rate so as to output constant length data words at a second data rate. An apparatus for decoding constant bit length data words into variable bit length data words shifts and concatenates the constant bit length data words, determines when a variable length data word is present in the concatenated data, supplies information about the number of bits in the variable length data words which is used when shifting the next constant bit length data word, and outputs variable bit length data words.

Abstract: The present invention teaches a control system wherein fiber optics controls the functioning of one or more types of wiring devices, such as a wall receptacle. With the use of the present invention, a relatively safer system is provided for use in wet, hospital, explosive and other environments, and which is capable of surface mounting. Switch and load supply assemblies are interconnected by fiber optic means for transmitting reflected signals from a movable mirror to a photocell-influenced relay circuit.

Abstract: An A/D converter comprises a first stage integrator for receiving an input signal, a last stage integrator, a multibit A/D converter connected to the output terminal of the last stage integrator, an outer feedback loop connected between the output terminal of the multi-bit A/D converter and the input terminal of said first stage integrator and having a 1-bit D/A converter, an inner feedback loop connected between the output terminal of the multibit A/D converter and the input terminal of the last stage integrator and having a multibit D/A converter, and a digital signal processing circuit, connected to the output terminal of the A/D converter, for performing digital signal processing of an output from the A/D converter to eliminate quantization noise caused by the outer feedback loop.

Abstract: Binary encoded information having a word size of 3N bits, where "N" is a positive integer, plus a parallel data clock are converted to corresponding control signals. Signal drivers with three-state outputs respond to the control signals and communicate corresponding signals via transmission lines, one transmission line per signal driver, to receiving circuits capable of detecting three-state signals, an embodiment of said circuits produce bipolar signals corresponding to the state of the transmission lines with which they communicate. A code converter produces binary signals and a data clock corresponding to the bipolar signals from the receiving circuits. The net result is that the binary word and data clock produced at a receiving end of the transmission lines logically matches the binary code and data clock applied at a sendng end, and that the produced data clock has the same timing relationship with the received binary word as does the originating data clock have with the originating binary word.

Abstract: A serial-parallel type A/D converter comprises first and second circuit blocks which are connected serially to operate in pipe lining. An input analogue signal is converted to a digital signal having highest significant bits at the first circuit block, and an analogue signal obtained by subtracting an analogue signal equal in value to the digital signal from the input analogue signal is converted at the second circuit block. The second circuit block is a recursive circuit block in which A/D converting operation is carried out for a plurality of cycles at the timing of several times faster than that of the first circuit block.

Abstract: A delta sigma modulator provides dual phase sampling of analog input and/or a reference voltage. This dual phase sampling may be realized using a switched capacitor circuit having dual legs with a capacitor on each such leg. The dual phase sampling of the reference voltage poses a complication that mandates the necessity of providing a compensation signal. The delta sigma modulator is provided with appropriate circuitry to provide a compensation signal that compensates for the reduced signal level due to the dual sampling. In particular, the delta sigma modulator compensates for the reduced level of the output from an integrating amplifier circuit due to the timing necessary to implement the dual sampling approach.

Abstract: In a sampling rate converter which converts a sampling frequency of digital signals sampled at a first sampling frequency into a second sampling frequency, output clocks corresponding to the second sampling frequency are counted in a cyclic fashion from an initial value to a maximum value based on periodicity of the first and second sampling frequencies. Coefficient addresses are generated in accordance with the resulting count value and a coefficient correction value which is determined in accordance with the number of counts of the maximum value and the periodicity of the first and second sampling frequencies, the number of counts of the maximum value being the number of times the output clocks are counted to the maximum value. The sampling frequency of digital signals sampled at the first sampling frequency is thus converted into the second sampling frequency with a simple construction of counting to the maximum value in accordance with the periodicity of the sampling frequencies.

Abstract: A controller has a data compression unit and error correcting code unit which share a single common random access memory. The controller is connected between a host computer and a peripheral device such as a tape drive. A second order search for strings of data bytes is enabled or disabled to change the compression ratio, data throughput, and memory bandwidth constraints.

Abstract: A signal digitizer for digitizing a continuous time varying input signal has a positive peak detector coupled to the input signal for storing the most positive peak value of the input signal and a negative peak detector coupled to the input signal for storing the most negative peak value of the input signal. Divider means are coupled to the outputs of the positive and negative peak detectors for producing a threshold voltage representative of a voltage between the outputs of the positive and negative peak detectors. A comparator has its inputs coupled to the threshold voltage and the input signal for producing a binary output signal in response to the relative values of its inputs. Limiter means are coupled to the outputs of the peak detectors for maintaining a maximum voltage potential between the peak detectors. Separator means are coupled to the outputs of the peak detectors for maintaining a minimum potential between the peak detectors regardless of the amplitude of the input signal.

Abstract: A technique for reducing the undesirable effects of amplifier offset voltages in quantizers such as analog-to-digital converters and related devices. The quantizer of the invention has an array of input amplifiers for comparing an input signal with multiple reference voltages, an array of latches for registering output signals from the amplifiers, and signal summing circuitry connected between the amplifiers and the latches, to produce a set of modified amplifier outputs for input to the latches, each of the modified amplifier outputs being derived from a weighted sum of at least three amplifier outputs. In the event of a defect in one or more amplifiers causing unwanted amplifier offsets, the summing circuitry improves linearity without the need for paralleling of transistor components. In one embodiment of the invention, the summing circuitry includes a resistor ladder to which the amplifier outputs are connected and from which the modified outputs are derived.

Abstract: A neural network quantizer for quantizing input analog signals includes a plurality of multi-level neurons. The input analog signals are sampled and supplied to respective ones of the multi-level neurons. Output values of the multi-level neurons are converted into analog values, weighted by weighting coefficients determined in accordance with a frequency band of at least one frequency component of the input analog signals and fed back to the respective one of the multi-level neurons and to the other multi-level neurons. The weighted analog values fed back are compared with the respective ones of the sampled input analog signals. The output values of the multi-level neurons are corrected in response to the compared results, and when the compared results are converged within a predetermined range, the output values of the multi-level neurons are produced to quantize the input analog signals.

Abstract: In a cell delineation circuit, an input signal is converted into parallel signals, and a plurality of parallel signals (i.e. series of parallel signals) which are shifted one bit by one bit from each other are formed from those parallel signals. CRC (Cyclic Redundancy Check) calculations are executed in parallel for the plurality of parallel signals. A series in which a pattern to be calculated satisfies a CRC rule is determined from results of the CRC calculations, and this series is generated, thereby establishing a cell delineation.

Abstract: Data compression and decompression utilizing, e.g., the Ziv-Lempel algorithm is simplified by utilizing a tree structure for the dictionary in which alternative symbols at a given position in a symbol sequence (a,b,c) are linked by linking pointers R of a first type and successive symbols (ab,bc,ca,aba,abb,abc) are linked by linking pointers D of a second type. For example, the sequence ab may continue with any one of the symbols a,b, and c grouped together by R pointers in a list below the final symbol of the sequence ab. Each symbol is defined by an associated pair of D and R pointers, in conjunction with a parent pointer P which identifies its parent. Symbols having no D pointers extending therefrom are pruned from the tree and transferred to a free list as shown in FIG. 8(b).

Abstract: An adaptive data compression and decompression system having a fixed dictionary size is disclosed. The compression system builds a data dictionary tree such that each path in the tree represents a string .omega., which was, along with its prefixes, in the input character stream being compressed. The root node and all nodes that do not represent a single character word in the input stream are tagged. Additionally, each non-root node is associated with a unique output code. As strings from the input stream of characters are matched against the tree, the node tags are updated. When a match fails, a new node is added. The new node is associated with a new code and a tag. When the dictionary is full, the root tag identifies the tag of a node that can be deleted. The decompression system builds a similar tapped decompression dictionary.

Abstract: A current generating device for generating two different currents having different magnitudes in response to corresponding one-bit data of digital data of a plurality of bits includes: NMOS transistors, (1,2,3), a control signal generating circuit and a supply circuit. The control signal generating circuit generates a voltage (V2) at which NMOS transistors (2,3) can be turned on and a voltage (V3) which is in the range between a ground potential and threshold values of the NMOS transistors and at which NMOS transistors (2,3) can be turned off. The supply circuit complementarily applies voltages (V1,V2) to NMOS transistors (2,3). NMOS transistor (1) generates a current with a predetermined magnitude. NMOS transistors (2,3) respond to voltages (V2, V3) to switch and allow/prevent passage of the predetermined-magnitude current generated by NMOS transistor (1).

Abstract: In an AC signal generating apparatus a digital sine wave signal of a set frequency, generated by a digital sine wave signal generating part, is converted by a D/A converter to an analog sine wave signal and is then output. The output sine wave signal is converted by an output detector to a voltage mean value, and the difference between it and a reference value is obtained by a comparator. The difference is negatively fed back, as a reference voltage, to the D/A converter to control its conversion gain so that the difference may approach zero. Thus, a highly accurate sine wave signal is obtained.

Abstract: A data conversion method and an apparatus for the same which converts undefined-length image signal coded by a MH or MR method for facsimile equipment, etc. into fixed-length data. Coded undefined-length image data is inputted, and, in accordance with a bit length contained in the image data and with the number of the effective bits in the last byte, bits to be outputted from a barrel shifter are shifted. Control is performed to byte pack the bits of the last byte and the shifted bits outputted from the barrel shifter, and coded data is converted into data in byte units, thereby enabling high-speed byte packing.