Abstract: A circuit for analog-to-digital conversion is disclosed comprising multiplexed ADCs. Dithering is introduced into the circuit before conversion and subtracted out of the resulting digital output stream. Gain control feedback loops are employed to eliminate non-unity gain error of the dither signal and multiplexed ADC differential gain errors. Correlation between the digital output stream and the dither signal is used to detect a non-unity condition and derive gain control feedback. Correlation with the dither signal is also used to detect gain differences between multiplexed ADCs and generate corrective feedback.

Abstract: A serial-to-parallel type A/D converter includes a resistance array, a plurality of comparators for upper bits, a plurality of comparators for lower bits, an encoder for upper bits, an encoder for lower bits and an adder. The resistance array divides a predetermined reference voltage to generate upper reference voltages, and by dividing the step width of the upper reference voltage, generates lower reference voltages. The plurality of comparators for the upper bits compare the analog input signal with the upper reference voltages, and applies the result of comparison to the encoder for the upper bits. The encoder for the upper bits calculates an estimated value of the upper bits based on the result of comparison, and select second reference voltages in the range provided by adding .+-.1/2 LSB to 1LSB corresponding to the estimated value of the upper bits. The plurality of comparators for the lower bits calculate the lower bits and a correcting bit based on the selected second reference voltages.

Abstract: A circuit compensates backlash of a shaft on an incremental encoder having a quadrature and index pulse output lines. Quadrature is represented as two signal lines phased apart by 90 degrees and an index pulse occurring once per revolution of the encoder shaft. The logical combination of the quadrature signals produce a four state condition which, through sequential examination of the signal levels, allows discriminating circuitry to determine the rotational direction of the encoder shaft. The circuit allows the definition of clockwise or counterclockwise rotation as being the forward direction. When the circuit discerns the positive forward rotational progression of the two signal lines, the circuit passes such signals unaltered to a pulse responsive system. Upon discernment of an encoder's shaft reverse rotation, the circuit causes the last forward rotational quadrature state to be latched on its output lines.

Abstract: A method and apparatus for testing an analog to digital converter (14) having a resistor digital to analog converter (32). In one form, the analog to digital converter uses a small amount of resistor test logic (44) to test for defects in the resistor array (42), the switch array (38), and the optional decode logic (36). Instead of performing time-consuming analog to digital conversions, the functionality of the above mentioned circuitry, which includes some analog circuitry, is tested by using a pull-up function and a pull-down function that can be overdriven by properly functioning circuitry. As a result of using resistor test logic (44), a very quick pass/fail functional test using digital logic levels as inputs can be performed on the analog to digital converter (14). The quick functional test does not require analog inputs or time-consuming analog to digital conversions.

Abstract: A data encoding system encodes data using the following d=7, k=2 code:______________________________________ DATA BITS CODE WORDS ______________________________________ 00 000X 01 0100 10 100X 011 10000X 111 100100 0000 1000000X ______________________________________where X is a ONE if the last two bits of the preceding code word are both ZEROS and a ZERO otherwise, and the right-most bits are the first in time. The system encodes the data by encoding the first four bits of data to an eight-bit code word if the bits are all ZEROS and the last two bits of the previous code word are in a predetermined pattern. If the first four bits are not ZEROS and the system encodes the first three data bits to form a six-bit code word if the first two bits are both ONES. Otherwise, the system encodes the first two data bits to form a four-bit code word. The system selects the code word which preserves the code limited run length.

Abstract: An improved integrating type A/D converter has a set of analog switches and a control logic unit for selectively connecting a pair of input terminals for an unknown analog input voltage signal with a pair of input leads across a buffer and integrator in order to apply, first in an integrate phase, the analog input signal in a polarity direction that causes the integrator to ramp up in the same direction regardless of the polarity of the analog input signal, and then in a deintegrate phase, reference voltages are applied across the input leads in a fixed direction opposite to the applied input voltage such that a zero crossing signal is output by the comparator. The ramping-up and ramping-down of the integrator in the same direction eliminates rollover error in the A/D reading of inputs of different polarities but of the same magnitude. The invention is particularly useful for monolithic A/D converters using BiMOS technology.

Abstract: In an A-D converter including a reference voltage generator, a D-A converter for outputting analog reference comparison voltage signals in response to digital signals; a comparator for comparing the voltages with an analog input voltage signal to be converted and outputting a reset signal when the voltage is substantially equal to the voltage, and a successive approximation register for successively outputting the digital signals to the D-A converter and an A-D converted signal in response to the reset signal, the D-A converter comprises in particular, at least one decoder block composed of plural array switches for coding any given function. Therefore, the analog input signal can be converted into the corresponding digital output signal in accordance with the coded function, thus providing an A-D converter suitable for use with a fuzzy controller. Further, the reference voltage generator is so configured as to easily change the coded membership function symmetrically or asymmetrically.

Abstract: A method and apparatus for generating correction signals for use in forming low distortion analog signals. A digital representation of a desired analog waveform is encoded into a digital data signal which is outputted to memory. A digital correction signal is encoded, having an opposite phase and increased amplitude from the signal distortion which it is determined will occur when the digital data signal is repetitively read out of memory and decoded. This digital correction signal is outputted to memory. The digital data and correction signals are repetitively and synchronously read out of memory into a decoder. The decoder converts both digital signals into analog signals, so that the analog correction signal may superpose on the distortion in the analog data signal, resulting in a low distortion analog signal.

Abstract: An N-bit interpolation analog/digital circuit comprises a first stage of p comparators (C.sub.1. . . C.sub.p). The outputs of the comparators are combined in a plurality of groups, which are connected so that the combined output (S.sub.1a, S.sub.1b) of each group has the shape of a signal periodically varying between high and low levels. The output voltages of each group are compared close to their zero crossings in second stages (I.sub.1. . . I.sub.r) of q+1 comparators each (p[q+1]=2.sup.N). Each comparator of the first stage is a high linearity comparator comprising two legs each comprising a first and a second transistor (T.sub.101, T.sub.102 ; T.sub.103, T.sub.104). The base of the second transistor of each leg is connected at the junction node of the transistors of the other leg through a voltage shifting means (E.sub.1, E.sub.2), and the emitters of the second transistors of each leg are interconnected through a resistor (RES).

Abstract: A structure and a method are provided for fast-decoding a Huffman code using a leading 1's detector for recognizing the number of leading 1's in the Huffman codeword up to a predetermined maximum, so as to provide a class number in accordance with the number of leading 1's recognized, a first logic circuit for providing a "remainder" by removing from the Huffman codeword a number of bits in accordance with the class number, and a second logic circuit for recognizing a special class. In one embodiment, decoding is accomplished by accessing a storage device using an address formed by a table number, a subclass number derived from the class number and all of the bits in the remainder except the least significant bit.

Abstract: A method and apparatus for compressing and decompressing text and image data by forming fixed-length codewords from a variable number of data symbols. Data symbols are shifted into registers in the first half of a buffer, while an uncompressed string of data symbols are shifted into registers in the second half of the buffer. A systolic array of processors compares each data symbol in the second half of the buffer with each data symbol in the first half of the buffer. Each processor compares pairs of data symbols, and selectively passes the data symbols to an adjacent processor. A fixed-length output is provided indicating the length and the starting point of the longest substring in the first half of the buffer that matches a substring from the second half of the buffer.

Abstract: The one-bit sigma-delta modulator with improved signal stability disclosed herein includes, in order, a first anti-aliasing filter (20), a chopper (22), a second anti-aliasing filter (30), and a one-bit modulator (32). The chopper (22) and one-bit modulator (32) are driven by a clock generator (38). The chopper (22) is introduced to provide a carrier upon which the signal may ride, thereby eliminating dc stability problems. The first anti-aliasing filter (20) eliminates aliasing from the chopper (22), and the second anti-aliasing filter (30) eliminates aliasing from the one-bit modulator (32). The second anti-aliasing filter (30) may be eliminated if the frequency of the chopper (22) is an exact integer submultiple of the sampling frequency of the one-bit modulator (32). This invention may drive a decimation filter (36), also driven by the clock generator (38), to provide a low cost analog-to-digital converter.

Abstract: A method and apparatus for testing an analog to digital converter (14) having a capacitor digital to analog converter (30). In one form, the analog to digital converter uses a small amount of capacitor test logic (44) to test for opens and shorts in the capacitor array (42), the switch logic (38), and the decode logic (36). Instead of performing time-consuming analog to digital conversions, the functionality of the above mentioned circuitry is tested by using AND and OR logical functions. As a result of using capacitor test logic (44), a very quick pass/fail functional test can be performed on the analog to digital converter (14) without requiring the analog to digital converter (14) to perform time-consuming analog to digital conversions.

Abstract: A digital code conversion system in a magnetic recording apparatus for converting one bit of an input digital signal into a signal of two bits, in which the number of binary digits of "0" making appearance between adjacent binary digits of "1" is two at minimum and seven at maximum. In the digital code resulting from the code conversion, ratio between maximum and minimum values of the density at which the binary digit of "1" makes appearance is 1:2.

Abstract: The present invention relates to a pulse width modulation (PWM) decoder, and more particularly to a PWM decoder which demodulates a pulse width modulated signal for proper interface with the operational characteristics of an object to be controlled. The present invention includes a PWM input terminal for receiving a PWM signal, an integrator for converting the PWM signal to a linear analog signal, and a transfer characteristic converter for changing the slope of the transfer characteristic of the integrator, so that a microcomputer can be interfaced with a signal processor without changing the microcomputer's internal design.

Abstract: A digital-to-analog (D/A) signal conversion device employing scaled field emission devices to convert a digital information multi-bit input signal including data information in one of many forms such as, for example, binary or decimal, to an analog output current or voltage signal.

Abstract: A two-frequency data signal, also known as a biphase or F/2F signal, is accurately decoded by sampling the signal and digitizing the samples to provide a series of digital values representing the signal. An intelligent digital filter manipulates the digital values to decode the signal, by detecting the peaks in the sampled signal and decoding the signal by analyzing the location and amplitudes of the peaks. Only peaks which are outside a guard band may be detected. If the signal cannot be properly decoded with a wide guard band, the guard band may be repeatedly narrowed, until a minimum guard band is reached.Bits are identified by comparing the displacements between peaks to a bit cell width. An even number of displacements indicates a `0` bit, and an odd number of displacements indicates a `1` bit.

Abstract: An analog-to-digital conversion module and method minimize software involvement by providing a programmable control table comprising a plurality of conversion command words (CCW's). Each CCW designates conversion parameters such as channel and reference selection, input sample time, and re-sample inhibit for one conversion operation, upon conclusion of which a digital value is stored in a corresponding result table. A set of CCW's defines one or more conversion sequences. Upon conclusion of each sequence, an interrupt can be issued and the result table may be read by an associated device, such as a CPU. If desired, the CCW sequence may be dynamically altered during operation of the conversion system.

Abstract: A variable length code encoder is provided in which, during variable length code encoding of video or audio data which has been divided into blocks for ease of transmission or storage, the lowest bit of a particular variable length code in each block of code words which is composed of a special pattern of bits and arranged to appear at no other position than the end of the block, is utilized for carrying a piece of data in addition to the data of the block.

Abstract: An analog-to-digital conversion system module comprises a pin-limited A/D converter integrated circuit (I.C.) to which at least one multiplexer I.C. may be coupled and sampled.In one embodiment, host system software involvement is minimized by providing a sequence of sample commands, implemented by a channel sequencer or a programmable control table comprising a plurality of conversion command words (CCW's). A set of CCW's defines a conversion sequence which may be initiated and performed with minimal host system software involvement, upon conclusion of which a result table storing the converted digital values may be read by an associated device, such as a CPU.In one embodiment, some I/O pins of the A/D converter I.C. function either as analog inputs or address outputs to the external multiplexer, while other analog input pins alternatively function as single input channels or as combined channels from one or more external multiplexers.