Patents Examined by Mardochee Chery
  • Patent number: 11410729
    Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: August 9, 2022
    Assignee: Kioxia Corporation
    Inventors: Suguru Nishikawa, Yoshihisa Kojima, Riki Suzuki, Masanobu Shirakawa, Toshikatsu Hida
  • Patent number: 11403040
    Abstract: A data programming method includes the following operations: assigning a first identity code to initial data according to a data type of the initial data; packing the first identity code, the initial data, and a check code to a new data packet; determining whether a first storage space in a flash memory stores a first data packet being the same as the new data packet; and if the first storage space does not store the first data packet, programming the new data packet to the first storage space in a first address sequence.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: August 2, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hao Zhou, Hong Chang, Xiao-Lin Luo
  • Patent number: 11397531
    Abstract: A method and apparatus for performing data protection regarding a non-volatile memory (NVM) are provided. The method includes: obtaining a first die-dependent seed and a second die-dependent seed, where the first die-dependent seed and the second die-dependent seed correspond to a die for implementing the NVM; performing rearrangement on multiple sets of address information of an address according to the first die-dependent seed, for protecting the address carried by at least one address signal between the controller and the NVM; and performing rearrangement on multiple subsets of a set of data according to the second die-dependent seed, for protecting the set of data carried by at least one data signal between the controller and the NVM.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: July 26, 2022
    Assignee: Realtek Semiconductor Corp.
    Inventor: Chang-Hsien Tai
  • Patent number: 11397689
    Abstract: A memory manager includes an internal memory and a hash function circuit. The internal memory includes a V2H (virtual address to hash function) table and an exception mapping table. The V2H table stores at least one virtual address group and a type information on a hash function mapped to the virtual address group. The exception mapping table stores at least one exception virtual address not translated into a physical address by the hash function in the virtual address group and a physical address mapped to the exception virtual address. The has function circuit checks, when a virtual address is provided from a host, type information on a hash function mapped to a virtual address group including the virtual address, by referring to the V2H table included in the internal memory. The has function translates the virtual address into a physical address by using the hash function corresponding to the type information.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: July 26, 2022
    Assignee: SK hynix Inc.
    Inventor: Kyu Hyun Choi
  • Patent number: 11392506
    Abstract: Examples include an apparatus which accesses secure pages in a trust domain using secure lookups in first and second sets of page tables. For example, one embodiment of the processor comprises: a decoder to decode a plurality of instructions including instructions related to a trusted domain; execution circuitry to execute a first one or more of the instructions to establish a first trusted domain using a first trusted domain key, the trusted domain key to be used to encrypt memory pages within the first trusted domain; and the execution circuitry to execute a second one or more of the instructions to associate a first process address space identifier (PASID) with the first trusted domain, the first PASID to uniquely identify a first execution context associated with the first trusted domain.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: July 19, 2022
    Assignee: INTEL CORPORATION
    Inventors: Vedvyas Shanbhogue, Ravi Sahita, Rajesh Sankaran, Siddhartha Chhabra, Abhishek Basak, Krystof Zmudzinski, Rupin Vakharwala
  • Patent number: 11392321
    Abstract: A memory system may include a plurality of nonvolatile memory devices, a first operation unit configured to perform a first operation on target data stored in target nonvolatile memory devices, and one or more second operation units configured to perform second operations. The first operation unit performs the first operation by reading target data and parity data from nonvolatile memory devices not associated with second operations concurrently performed by the second operation units.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: July 19, 2022
    Assignee: SK hynix Inc.
    Inventors: Duk Joon Jeon, Jong Ryool Kim
  • Patent number: 11392425
    Abstract: Technologies for utilizing a split memory pool include a compute sled. The compute sled includes multiple processors communicatively coupled together through a processor communication link. Each processor is to communicate with a different memory sled through a respective memory network dedicated to the corresponding processor and memory sled. The compute sled includes a compute engine to generate a memory access request to access a memory address in far memory. The far memory includes memory located on one of the memory sleds. The compute engine is also to determine, as a function of the memory address and a map of memory address ranges to the memory sleds, the memory sled on which to access the far memory, and send the memory access request to the determined memory sled to access the far memory associated with the memory address.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: July 19, 2022
    Assignee: Intel Corporation
    Inventors: Mark A. Schmisseur, Aaron Gorius
  • Patent number: 11385997
    Abstract: There are provided a controller, a memory system having the same, and an operating method thereof. The controller includes a read counter configured to store a block read count value of a super block and memory blocks within a non-super block as a status information in an internal memory by counting a number of times that a read operation is performed on the memory blocks; and a super block manager configured to: store a super block reclaim trigger reference and a non-super block reclaim trigger reference, which is set for the super block and the non-super block, as the status information in the internal memory, divide data stored in the memory blocks into hot data and cold data according to the block read count value, and copy the hot data in the non-super block to the super block according to the status information.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: July 12, 2022
    Assignee: SK hynix Inc.
    Inventor: Hye Mi Kang
  • Patent number: 11386024
    Abstract: According to certain embodiments, a memory module is operable with a memory controller of a host system. The memory module includes a module controller configurable to receive address and control signals from the memory controller, and dynamic random access memory elements configurable to communicate data signals with the memory controller in accordance with the address and control signals. The module controller has an open-drain output and is configurable to drive the open-drain output with a first signal to indicate a parity error having occurred when the memory module is being accessed for a normal memory read or write operation. The module controller is further configurable to drive the open drain output with a second signal related to one or more training sequences when the memory module performs operations associated with the one or more training sequences and not associated with any normal memory read or write operations.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: July 12, 2022
    Assignee: Netlist, Inc.
    Inventor: Hyun Lee
  • Patent number: 11379128
    Abstract: Systems, storage devices, and methods for application-based storage device configuration settings are described. A storage device may receive a storage command and dynamically select an application set of configuration settings for processing the storage command, where the configuration settings include trim parameters for writing data units to the storage medium of the storage device.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: July 5, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Dinesh Kumar Agarwal, Amit Sharma
  • Patent number: 11379411
    Abstract: A system and method for replicating a file system. The method includes: copying a portion of the file system from a first storage, wherein the at least a portion of the file system includes underlying data and metadata, wherein the metadata includes pointers to the underlying data and metadata defining a file system hierarchy; partitioning the copied data of the file system into a plurality of blobs, wherein the plurality of blobs includes a plurality of data blobs and a plurality of metadata blobs, wherein each data blob includes at least one portion of the underlying data; generating a plurality of filter objects based on the copied data, wherein each filter object includes a list of metadata blobs; and storing the plurality of blobs and the plurality of filter objects in a second storage.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: July 5, 2022
    Assignee: Vast Data Ltd.
    Inventors: Vladimir Zdornov, Asaf Levy, Asaf Weissman, Or Dahan, Hillel Costeff
  • Patent number: 11379129
    Abstract: A FPGA-based intelligent storage control system is provided that includes a FLASH main controller; a FLASH command former and an address generator with a memory function, for generating level signal of cross clock domain and automatically avoiding out-of-bounds writing. A configuration data former provides for driving and controlling a configuration writing in function by a writing configuration drive signal. An automatic reading configurator provides automatic configuration reading by internal drive signal to drive. A main data and auxiliary data former provides continuous storage of main data according to ping-pong operation for unequal width RAM operation. A FLASH data reading buffer and a multi-interface external drive module are also present. The system is applicable to an unmanned underwater vehicle and underwater acoustic equipment.
    Type: Grant
    Filed: December 24, 2020
    Date of Patent: July 5, 2022
    Assignee: SHANGHAI ACOUSTICS LABORATORY, CHINESE ACADEMY OF SCIENCES
    Inventors: Feng Hong, Haihong Feng, Minyan Huang
  • Patent number: 11366767
    Abstract: In one embodiment, the method includes receiving, at a storage device, a request. The request includes a request message authentication code and write protect information. The write protect information includes at least one of start address information and length information. The start address information indicates a logical block address at which a memory area in a non-volatile memory of the storage device starts, and the length information indicates a length of the memory area. The method also includes generating, at the storage device, a message authentication code based on (1) at least one of the start address information and the length information, and (2) a key stored at the storage device; authenticating, at the storage device, the request based on the generated message authentication code and the request message authentication code; and processing, at the storage device, the request based on a result of the authenticating.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: June 21, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaegyu Lee, Jisoo Kim, Young-Jin Park, Bo-Ram Shin
  • Patent number: 11366612
    Abstract: According to one embodiment, a memory system writes first write data into each non-defective physical block belonging to a first write destination block group. The memory system notifies a host of a first identifier of the first write data, an address specifying the first write destination block group, a first offset indicating a top write destination physical storage location in the first write destination block group in which the first write data is written, length of the first write data, and first bitmap information including a plurality of bits, each of the bits corresponding to each of physical blocks belonging to the first write destination block group and indicating whether or not the corresponding physical block is a defective block.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: June 21, 2022
    Assignee: Kioxia Corporation
    Inventors: Shinichi Kanno, Takehiko Kurashige
  • Patent number: 11360912
    Abstract: A method for performing adaptive locking range management, an associated data storage device and a controller thereof are provided. The method may include: receiving a security command from outside of the data storage device, wherein the security command is related to changing an old locking range into a new locking range; obtaining a start Logical Block Address (LBA) and a length value of the new locking range according to the security command; determining whether the start LBA of the new locking range is less than an end LBA of the old locking range, and determining whether an end LBA of the new locking range is greater than a start LBA of the old locking range; and in response to both determination results being true, performing data trimming on any respective non-overlapped portions of the new locking range and the old locking range.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: June 14, 2022
    Assignee: Silicon Motion, Inc.
    Inventors: Chih-Yu Lin, Hung-Ting Pan, Sung-Ling Hsu
  • Patent number: 11354253
    Abstract: In one embodiment, the method includes receiving, at a storage device, a request. The request includes a request message authentication code and write protect information. The write protect information includes at least one of start address information and length information. The start address information indicates a logical block address at which a memory area in a non-volatile memory of the storage device starts, and the length information indicates a length of the memory area. The method also includes generating, at the storage device, a message authentication code based on (1) at least one of the start address information and the length information, and (2) a key stored at the storage device; authenticating, at the storage device, the request based on the generated message authentication code and the request message authentication code; and processing, at the storage device, the request based on a result of the authenticating.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: June 7, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaegyu Lee, Jisoo Kim, Young-Jin Park, Bo-Ram Shin
  • Patent number: 11354056
    Abstract: A computing system having memory components of different tiers. The computing system further includes a controller, operatively coupled between a processing device and the memory components, to: receive from the processing device first data access requests that cause first data movements across the tiers in the memory components; service the first data access requests after the first data movements; predict, by applying data usage information received from the processing device in a prediction model trained via machine learning, second data movements across the tiers in the memory components; and perform the second data movements before receiving second data access requests, where the second data movements reduce third data movements across the tiers caused by the second data access requests.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: June 7, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Samir Mittal, Anirban Ray, Gurpreet Anand
  • Patent number: 11347606
    Abstract: Determining active membership among a set of storage systems synchronously replicating a dataset, where determining active membership includes: determining that a membership event corresponds to a change in membership to the set of storage systems synchronously replicating the dataset; applying, in dependence upon the membership event, one or more membership protocols to determine a new set of storage systems to synchronously replicate the dataset; and for one or more I/O operations directed to the dataset, applying the one or more I/O operations to the dataset synchronously replicated by the new set of storage systems.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: May 31, 2022
    Assignee: Pure Storage, Inc.
    Inventors: Connor Brooks, Thomas Gill, David Grunwald, Ronald Karr, Aswin Karumbunathan, Naveen Neelakantam, Zoheb Shivani, Kunal Trivedi
  • Patent number: 11347424
    Abstract: Systems and methods for processing data segments are disclosed. In one embodiment, such functionality includes buffering data received from a node (where the data is stored in a buffer as buffered data, an offset value is associated with the data, and a segment size is associated with the buffer), and determining whether the offset value is an integer multiple of the segment size. In response to determination that the offset value is an integer multiple of the segment size, processing the data in the buffer as a segment. Such functionality also includes determining whether the segment is a duplicate of data stored in a deduplicated data store and, in response to a determination that the segment is not a duplicate of data stored in the deduplicated data store, storing the segment in the deduplicated data store.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: May 31, 2022
    Assignee: VERITAS TECHNOLOGIES LLC
    Inventors: Xianbo Zhang, Yong Yang
  • Patent number: 11340833
    Abstract: Methods, systems, and devices related to data relocation via a cache are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In some cases, the memory device may transfer data from a first address of the memory array to the signal development cache. The memory device may transfer the data stored in the signal development cache to a second address of the memory array based on a parameter associated with the first address of the memory array satisfying a criterion for performing data relocation.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: May 24, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Shanky Kumar Jain, Dmitri A. Yudanov