Abstract: Systems, methods, circuits, and devices for managing data transfers in semiconductor devices are provided. In one aspect, an integrated circuit includes: a first interface for receiving higher-speed-type data, a second interface for receiving lower-speed-type data, a first logic circuit coupled to the first interface, a second logic circuit coupled to the second interface, and a driving circuit separately coupled to the first logic circuit and the second logic circuit. The first data interface, the first logic circuit, and the driving circuit are arranged in series to form a first data path for transferring the higher-speed-type data with a first speed. The second data interface, the second logic circuit, and the driving circuit are arranged in series to form a second data path for transferring the lower-speed-type data with a second speed. The first speed is higher the second speed.

Abstract: Techniques for data processing involve: performing, according to a determination that a programmable circuit receives user-written data, data feature detection by the programmable circuit on a first part of the user-written data. Such techniques further involve: replacing, in response to the first part matching a predetermined data feature, the first part by the programmable circuit with a data representation corresponding to the predetermined data feature. In addition, such techniques involve: writing the data representation to a cache region of a storage system. Accordingly, such techniques can save cache resources of a storage system and can save CPU of the storage system, thus avoiding the latency due to data feature detection and improving the user experience.

Abstract: Disclosed are a method and a system for data uploading, which belongs to the technical field of blockchain. The method comprises: receiving a block upload request sent by a slave server of a target node; determining whether block data corresponding to the block upload request has been uploaded to a block data storage system; if the block data corresponding to the block upload request is not uploaded to the block data storage system, acquiring the block data if the block data corresponding to the block upload request is not uploaded to the block data storage system, and uploading the block data to a storage space of the block data storage system; and sending an uploading success instruction to the slave server if the uploading is successful, so as to instruct the slave server to delete the block data stored on a light-weight peer in the target node.

Abstract: An apparatus and method for dispatching flash commands. The apparatus includes a plurality of queues, wherein each queue comprises an input to receive a flash command, an output to send a flash command, and an empty signal output to signal when the queue is empty, wherein each queue is assigned a unique, ordered priority. The apparatus includes a selector comprising a plurality of flash command inputs, a flash command output to a flash target, and a selection input, wherein each flash command input is coupled to a corresponding queue output. The apparatus includes an arbiter comprising inputs receiving each queue empty signal and receiving a lock bit from the flash command output of the selector and comprising a selection output coupled to the selection input of the selector. The flash command comprises a lock bit and a plurality of control bits to output to control inputs on a flash target.

Abstract: Methods, devices, and systems for retrieving information based on cache miss prediction. It is predicted, based on a history of cache misses at a private cache, that a cache lookup for the information will miss a shared victim cache. A speculative memory request is enabled based on the prediction that the cache lookup for the information will miss the shared victim cache. The information is fetched based on the enabled speculative memory request.

Abstract: A degree of fragmentation is determined based on a number of holes present in a storage system layout or a portion of a layout. Edges between the holes and used portions of the storage system are tabulated by scanning a storage space. The occurrences of a pattern of used/available allocation units and/or the occurrences of another pattern available/used allocation units are recognized. A fragmentation value is calculated based on occurrences of the patterns in view of the total storage space. The present fragmentation measurement system utilizes the number of occurrences of the holes in assessing fragmentation.

Abstract: A system includes a memory device and a processing device communicatively coupled to the memory device. The processing device is to write data to a number of groups of memory cells of the memory device in a physically non-contiguous manner. The processing device is further to track a sequence in which the number of groups of memory cells were written with the data. In response to a trigger event, the processing device is further to identify at least a portion of the number of groups of memory cells having data received over a predefined period preceding the trigger event based at least in part on the tracked sequence.

Abstract: A method for improving message storage efficiency of a network chip, a device, and a storage medium are provided. The method comprises: configuring a data memory, dividing the data memory into N small RAMs, and managing respective RAMs by means of a link list; in a case where a write data request is received on any input interface, parsing and acquiring a channel number corresponding to the input interface, accessing a channel write state memory according to the channel number to acquire channel write state information, in a case of determining, according to the channel write state information, that at least one RAM is null, writing data into the data memory; and in a case where a read-out scheduling request is received on any channel, recombining data according to memory information in a link list memory and reading the recombined data out.

Abstract: A storage device includes a communication circuit and a controller. The controller is configured to transmit log data to a host device through the communication circuit in response to receiving a first signal from the host device, receive a second signal, including an operation condition of an algorithm of the storage device, from the host device through the communication circuit, and change the operation condition of the algorithm on the basis of the second signal, wherein the algorithm includes one or more instructions for controlling an operation of the storage device.

Abstract: Taking recovery actions for replicated datasets, including: determining whether a request to modify a dataset that is synchronously replicated among a plurality of storage systems has been applied on a particular storage system of the plurality of storage systems, wherein the plurality of storage systems is synchronously replicating the dataset by acknowledging the request as being complete when each storage system has modified its copy of the dataset; and applying a recovery action based on whether the request to modify the dataset has been applied on the particular storage system of the plurality of storage systems.

Abstract: A non-volatile memory system separately performs a memory operation for multiple sub-blocks of a block in order from previously determined slowest sub-block of the block to a previously determined faster sub-block of the block. As a slower sub-block is more likely to fail, this order of is more likely to identify a failure earlier in the process thereby saving time and reducing potential for a disturb. In some embodiments, the proposed order of operation can be used in conjunction with a programming process that concurrently programs blocks in multiple planes using completion of programming of a fastest plane to a data state as a trigger to test for program failure of other planes to the data state.

Abstract: Some areas (e.g., boundary wordlines) in a block of memory can be more error prone than others. Typically, errors in these areas are not detected until after the entire block is programmed. Handling such errors then can result in performance penalties and large data relocations. With the embodiments presented herein, a two-stage programming operation is provided. In the first stage, only the error-prone areas of the block are programmed, and a check is made to determine if an error occurred in that programming. In the second stage, the remaining portions of the block are programmed, but that only occurs after it is determined that the error-prone areas have been programmed successfully. Detecting and dealing with errors in the error-prone areas before the entire block is programmed avoid the performance penalties and large data relocations noted above.

Abstract: Embodiments of the present disclosure relate to memory page access instrumentation for generating a memory access profile. The memory access profile may be used to co-locate data near the processing unit that accesses the data, reducing memory access energy by minimizing distances to access data that is co-located with a different processing unit (i.e., remote data). Execution thread arrays and memory pages for execution of a program are partitioned across multiple processing units. The partitions are then each mapped to a specific processing unit to minimize inter-partition traffic given the processing unit physical topology.

Abstract: A memory device controller for a non-volatile memory device can be configured to allow exclusive access to initiate or increment a refresh routine based on an earlier-received one of a refresh command from a host device or an interval-triggered refresh command from the controller. The memory device controller can be configured to lock out access to the refresh routine from a later-received one of the refresh command from the host device or the interval-triggered refresh command from the controller. The memory device controller can release a lock on access to the refresh routine upon completion of a block refresh routine for a memory block of the memory device. In some examples, the refresh command from the host device can be based on a power cycle status of the host device.

Abstract: A technique for operating a cache is disclosed. The technique includes utilizing a first portion of a cache in a directly accessed manner; and utilizing a second portion of the cache as a cache.

Abstract: A technique for managing a log in a storage system includes adding descriptors to the log, the descriptors indicating changes in user data that affects metadata, and creating a working set of descriptors that includes both per-block descriptors for specifying per-block changes and per-extent descriptors for specifying per-extent changes, where an extent includes a range of contiguous blocks. The technique further includes flushing the working set in a single flush cycle, including flushing the per-block descriptors together with the per-extent descriptors.

Abstract: A memory controller includes an arbiter, a vector arithmetic logic unit (VALU), a read buffer and a write buffer both coupled to the VALU, and an atomic memory operation scheduler. The VALU performs scattered atomic memory operations on arrays of data elements responsive to selected memory access commands. The atomic memory operation scheduler is for scheduling atomic memory operations at the VALU; identifying a plurality of scattered atomic memory operations with commutative and associative properties, the plurality of scattered atomic memory operations on at least one element of an array of data elements associated with an address; and commanding the VALU to perform the plurality of scattered atomic memory operations.

Abstract: A storage system is provided. The storage system includes a first storage cluster, the first storage cluster having a first plurality of storage nodes coupled together and a second storage cluster, the second storage cluster having a second plurality of storage nodes coupled together. The system includes an interconnect coupling the first storage cluster and the second storage cluster and a first pathway coupling the interconnect to each storage cluster. The system includes a second pathway, the second pathway coupling at least one fabric module within a chassis to each blade within the chassis.

Abstract: In some examples, a computer system computes a rate of operations that involves a first system, and classifies, using a classifier, a request for an operation. The computer system determines a relationship between the computed rate of operations and a dynamic threshold rate determined during a training phase, and based on the determined relationship and a classification of the request by the classifier, selectively activates or disables an operational feature of the first system.

Abstract: A data transfer device including an enclosure with a plurality of input/output connection ports, a processor, a memory including a data store, and a data transfer component. The data transfer component directs the processor to transfer data from an external data source via at least one of the plurality of input/output connection ports, encrypt the transferred data, store the encrypted data on the data store, responsive to a successful transfer of the encrypted data to the data store, delete the data from the external data source, establish a connection to an external data storage service, responsive to a successful connection to the external data storage service, transfer the encrypted stored data to the external data storage service, responsive to a successful transfer of the encrypted stored data to the external data storage service, deleting the encrypted stored data from the data store.