Patents Examined by Mardochee Chery
  • Patent number: 10818358
    Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: October 27, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Suguru Nishikawa, Yoshihisa Kojima, Riki Suzuki, Masanobu Shirakawa, Toshikatsu Hida
  • Patent number: 10802743
    Abstract: A control plane for controlling transfer of data to a data plane is disclosed. In one aspect, the control plane comprises memory cells for storing a digitally coded parameter value and having a data input electrode, a data output electrode and a control electrode, n data input terminals that receive a data input value and apply it to the data input electrode of an associated memory cell, and n data output terminals coupled to a data output electrode of an associated memory cell. The control plane further comprise a first delay line having delay elements and arranged for receiving a stream of control bit values, and a second delay line having delay elements and arranged for receiving a signal for enabling the control bit values in the first delay line, wherein data is transferred in a controlled and synchronized fashion to an output electrode.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: October 13, 2020
    Assignees: IMEC vzw, Katholieke Universiteit Leuven
    Inventors: Francky Catthoor, Praveen Raghavan, Daniele Garbin, Dimitrios Rodopoulos, Odysseas Zografos
  • Patent number: 10788997
    Abstract: A method and device for storage management comprising: in response to receiving a request for creating an extent pool, creating the extent pool at least on a user disk, the extent pool comprising a plurality of disk extents; storing data in at least one disk extent of the plurality of disk extents; and storing address information for locating the at least one disk extent in a system disk communicably connected to the user disk. Through the technical solution of the present disclosure, the user can store metadata associated with RAID in the user disk and load metadata associated with RAID from the user disk so as to reduce the access and load of the system disk.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: September 29, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Shaoqin Gong, Hongpo Gao, Jian Gao, Jamin Jianbin Kang, Ree Lei Sun
  • Patent number: 10789018
    Abstract: A primary copy and one or more shadow copies of a logical volume are created and discovered by a host rescan performed when the logical volume is initially created. Data storage resources are allocated to the primary copy, but not to the shadow copy. The initial path state of the logical volume describes the path to the primary copy as active, and the path to the shadow copy as unavailable for accessing the logical volume. Movement of the logical volume to the storage appliance providing the shadow copy can be performed without an additional host rescan, by making the shadow copy the new primary copy, making the primary copy a new shadow copy, and updating the path state of the logical volume to indicate i) that the path to the new primary copy is active, and ii) that the path to the new shadow copy is unavailable.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: September 29, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Dmitry Tylik, Matthew H. Long, Daniel E. Cummins, Nagasimha Haravu, Kenneth Hu, Matthew Eaton, Matthew Jean
  • Patent number: 10783090
    Abstract: In one embodiment, the method includes receiving, at a storage device, a request. The request includes a request message authentication code and write protect information. The write protect information includes at least one of start address information and length information. The start address information indicates a logical block address at which a memory area in a non-volatile memory of the storage device starts, and the length information indicates a length of the memory area. The method also includes generating, at the storage device, a message authentication code based on (1) at least one of the start address information and the length information, and (2) a key stored at the storage device; authenticating, at the storage device, the request based on the generated message authentication code and the request message authentication code; and processing, at the storage device, the request based on a result of the authenticating.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: September 22, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaegyu Lee, Jisoo Kim, Young-Jin Park, Bo-Ram Shin
  • Patent number: 10782908
    Abstract: A computing system having memory components of different tiers. The computing system further includes a controller, operatively coupled between a processing device and the memory components, to: receive from the processing device first data access requests that cause first data movements across the tiers in the memory components; service the first data access requests after the first data movements; predict, by applying data usage information received from the processing device in a prediction model trained via machine learning, second data movements across the tiers in the memory components; and perform the second data movements before receiving second data access requests, where the second data movements reduce third data movements across the tiers caused by the second data access requests.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: September 22, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Samir Mittal, Anirban Ray, Gurpreet Anand
  • Patent number: 10761996
    Abstract: Examples include an apparatus which accesses secure pages in a trust domain using secure lookups in first and second sets of page tables. For example, one embodiment of the processor comprises: a decoder to decode a plurality of instructions including instructions related to a trusted domain; execution circuitry to execute a first one or more of the instructions to establish a first trusted domain using a first trusted domain key, the trusted domain key to be used to encrypt memory pages within the first trusted domain; and the execution circuitry to execute a second one or more of the instructions to associate a first process address space identifier (PASID) with the first trusted domain, the first PASID to uniquely identify a first execution context associated with the first trusted domain.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Vedvyas Shanbhogue, Ravi Sahita, Rajesh Sankaran, Siddhartha Chhabra, Abhishek Basak, Krystof Zmudzinski, Rupin Vakharwala
  • Patent number: 10754768
    Abstract: A memory system includes a nonvolatile memory device; In an embodiment, a memory system comprising: a nonvolatile memory device; a working memory configured to store a first layer and a second layer as firmwares, each of which drives the nonvolatile memory device; a control component configured to control the nonvolatile memory device based on the firmwares; a buffer memory configured to store a first table which is managed by the first layer and a second table which is managed by the second layer; and a memory controller configured to store a descriptor for setting information of the nonvolatile memory device, and interface with the nonvolatile memory device based on control of the control component, wherein the second layer stores position information of the descriptor in the second table, and wherein the first layer accesses the memory controller by referring to the second table.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: August 25, 2020
    Assignee: SK hynix Inc.
    Inventor: Joo Young Lee
  • Patent number: 10754551
    Abstract: A method and associated systems for a workload-aware thin-provisioning system that allocates physical storage to virtual resources from pools of physical storage volumes. The system receives constraints that limit the amount of storage that can be allocated from each pool and the total workload that can be directed to each pool. It also receives lists of previous workloads and allocations associated with each volume at specific times in the past. The system then predicts future workloads and allocation requirements for each volume by regressing linear equations derived from the received data. If the predicted values indicate that a pool will at a future time violate a received constraint, the system computes the minimum costs to move each volume of the offending pool to a less-burdened pool. It then selects the lowest-cost combination of volume and destination pool and then moves the selected volume to the selected pool.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: August 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: John J. Auvenshine, Rakesh Jain, James E. Olson, Mu Qiao, Ramani R. Routray, Stanley C. Wood
  • Patent number: 10747465
    Abstract: A technique preserves replication to a storage node. The technique involves, from a first storage node, sending a replication query to a second storage node. The technique further involves, in response to the replication query sent to the second storage node, receiving replication session data from the second storage node. The replication session data describes replication which has terminated from a third storage node to the second storage node for a particular storage object. The technique further involves, based on the replication session data, establishing replication from the first storage node to the second storage node for the particular storage object to preserve use of the particular storage object.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: August 18, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Qiu Shang, Vasu Subramanian, Qi Qu, Tianfang Xiong, Yue Qian
  • Patent number: 10747687
    Abstract: In one embodiment, the method includes receiving, at a storage device, a request. The request includes a request message authentication code and write protect information. The write protect information includes at least one of start address information and length information. The start address information indicates a logical block address at which a memory area in a non-volatile memory of the storage device starts, and the length information indicates a length of the memory area. The method also includes generating, at the storage device, a message authentication code based on (1) at least one of the start address information and the length information, and (2) a key stored at the storage device; authenticating, at the storage device, the request based on the generated message authentication code and the request message authentication code; and processing, at the storage device, the request based on a result of the authenticating.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: August 18, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaegyu Lee, Jisoo Kim, Young-Jin Park, Bo-Ram Shin
  • Patent number: 10732870
    Abstract: A method and an apparatus for triggering RAID reconstruction are disclosed, to achieve high universality and usability in triggering RAID reconstruction. The method includes: obtaining valid data information of a target storage medium after a change in storage mediums in a RAID is detected (S101); and reconstructing the RAID if the valid data information satisfies a preset reconstruction condition (S102).
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: August 4, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Defu Liao, Guannan Zhang, Lin Peng
  • Patent number: 10725927
    Abstract: Aspects of the present disclosure describe a cache system that is co-managed by software and hardware that obviates use of a cache coherence protocol. In some embodiments, a cache would have the following two hardware interfaces that are driven by software: (1) invalidate or flush its content to the lower level memory hierarchy; (2) specify memory regions that can be cached. Software would be responsible for specifying what regions can be cacheable, and may flexibly change memory from cacheable and not, depending on the stage of the software program. In some embodiments, invalidation can be done in one cycle. Multiple valid bits can be kept for each tag in the memory. A vector “valid bit vec” comprising a plurality of bits can be used. Only one of two bits may be used as the valid bit to indicate that this region of memory is holding valid information for use by the software.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: July 28, 2020
    Assignee: Beijing Panyi Technology Co., Ltd.
    Inventor: Xingzhi Wen
  • Patent number: 10725706
    Abstract: A method of scheduling universal flash storage (UFS) operations using a refresh handover mechanism is described. The method includes receiving, during refresh of a UFS device, a request for an input/output (I/O) operation. The method also includes handing over between a first type of refresh operation and a second type of refresh operation in response to the request for the I/O operation.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: July 28, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Madhu Yashwanth Boenapalli, Hyunsuk Shin, Surendra Paravada, Sai Praneeth Sreeram, Venu Madhav Mokkapati
  • Patent number: 10712946
    Abstract: Systems and methods can implement one or more intelligent caching algorithms that reduce wear on the SSD and/or to improve caching performance. Such algorithms can improve storage utilization and I/O efficiency by taking into account the write-wearing limitations of the SSD. Accordingly, the systems and methods can cache to the SSD while avoiding writing too frequently to the SSD to increase or attempt to increase the lifespan of the SSD. The systems and methods may, for instance, write data to the SSD once that data has been read from the hard disk or memory multiple times to avoid or attempt to avoid writing data that has been read only once. The systems and methods may also write large chunks of data to the SSD at once instead of a single unit of data at a time. Further, the systems and methods can write to the SSD in a circular fashion.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: July 14, 2020
    Assignee: Commvault Systems, Inc.
    Inventors: Amit Mitkar, Andrei Erofeev
  • Patent number: 10691598
    Abstract: A method for managing cache memory in a user device is disclosed. The method comprises stagewise excluding adding data to the cache memory as cache memory fill level increases, the stagewise excluding comprising determining, for each successive stage of cache memory fill level, exclusion of the data from being added to the cache memory according to rules of exclusion of adding of data to the cache memory that are increasingly restrictive.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: June 23, 2020
    Assignee: INTERDIGITAL CE PATENT HOLDINGS
    Inventors: Thierry Quere, Renaud Rigal, Florent Fresnaye
  • Patent number: 10691367
    Abstract: A computer-implemented method of information lifecycle management is disclosed. The computer-implemented method includes reading, by a data processing system of a storage environment, business rules and policies for managing data in storage volumes of the storage environment, the policies being based on the predetermined business rules, and analyzing, by the data processing system, available storage and capacity in the storage environment. The computer-implemented method further includes dynamically prioritizing, by the data processing system, the policies based, at least in part, on results of the analyzing, resulting in prioritized policies, cognitively translating, by the data processing system, one or more of the predetermined business rules into action(s) against one or more of the storage volumes based, at least in part, on the prioritized policies, and executing, by the data processing system, the action(s).
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: June 23, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John J. Auvenshine, David Schustek, Tron H. Pryor, Luis Ignacio Callero, Laura Richardson, Robert Ong Sio, David Lutz, Dave Aime Desire Kodjo
  • Patent number: 10678476
    Abstract: A memory system and an operating method thereof are provided. The memory system includes a controller buffer memory, a host interface configured to receive non-linear host physical addresses and write data from a host, a host address translation section configured to map the non-linear host physical addresses to linear virtual addresses, and a host control section configured to buffer the write data in the controller buffer memory according to the linear virtual addresses.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: June 9, 2020
    Assignee: SK hynix Inc.
    Inventor: Dong Sop Lee
  • Patent number: 10671305
    Abstract: Various systems and methods are disclosed for optimizing data segments used during inline data deduplication, among other features and functionality. In one embodiment, such functionality includes buffering data received from a node, where an offset value is associated with the data and a segment size is associated with the buffer, until the buffer becomes full or a trigger event occurs. In response to determining that the buffer is full or that a trigger event has occurred, determining whether the offset value is an integer multiple of the segment size. If the offset value is not an integer multiple of the segment size, the functionality generates a modified segment, and then determines whether that modified segment is a duplicate of data stored in a deduplicated data store. If the modified segment is not a duplicate, the modified segment is stored in the deduplicated data store.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: June 2, 2020
    Assignee: Veritas Technologies LLC
    Inventors: Xianbo Zhang, Yong Yang
  • Patent number: 10664199
    Abstract: A processor includes a processing core to generate a memory request for an application data in an application. The processor also includes a virtual page group memory management (VPGMM) unit coupled to the processing core to specify a caching priority (CP) to the application data for the application. The caching priority identifies importance of the application data in a cache.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Subramanya R. Dulloor, Rajesh M. Sankaran, David A. Koufaty, Christopher J. Hughes, Jong Soo Park, Sheng Li