Patents Examined by Maria Ligai
  • Patent number: 10066936
    Abstract: An article is presented configured for controlling a multiple patterning process, such as a spacer self-aligned multiple patterning, to produce a target pattern. The article comprises a test site carrying a test structure comprising at least one pair of gratings, wherein first and second gratings of the pair are in the form of first and second patterns of alternating features and spaces and differ from the target pattern by respectively different first and second values which are selected to provide together a total difference such that a differential optical response from the test structure is indicative of a pitch walking effect.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: September 4, 2018
    Assignee: NOVA MEASURING INSTRUMENTS LTD
    Inventor: Igor Turovets
  • Patent number: 10043767
    Abstract: A method is disclosed that includes the operations outlined below. A plurality of dummy conductive cells that provide different densities are formed in a plurality of empty areas in a plurality of metal layers of a semiconductor device according to overlap conditions of the empty areas between each pair of neighboring metal layers.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: August 7, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Wei-Yu Ma, Hui-Mei Chou, Kuo-Ji Chen
  • Patent number: 10038104
    Abstract: A junction field-effect transistor (JFET) with a gate region that includes two separate sub-regions having material of different conductivity types and/or a Schottky junction that substantially suppresses gate current when the gate junction is forward-biased, as well as complementary circuits that incorporate such JFET devices.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: July 31, 2018
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Patent number: 10008561
    Abstract: A semiconductor device including a first circuit region in which a first circuit whose power supply potential is a first voltage is formed; a second circuit region in which a second circuit whose power supply potential is a second voltage lower than the first voltage is formed a separation region which separates the first circuit region from the second circuit region; and a transistor which is located in the separation region and couples the second circuit to the first circuit and whose source and drain are of a first conductivity type, the separation region including an element separation film; a first field plate which overlaps with the element separation film in plan view; a plurality of conductive films which are provided over the first field plate.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: June 26, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshinori Kaya, Yasushi Nakahara, Ryo Kanda, Tetsu Toda
  • Patent number: 9972685
    Abstract: A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion. The superlattice punch-through layer may include a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Each fin may also include an upper semiconductor fin portion on the at least one superlattice punch-through layer and extending vertically upward therefrom. The semiconductor device may also include source and drain regions at opposing ends of the fins, and a gate overlying the fins.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: May 15, 2018
    Assignee: ATOMERA INCORPORATED
    Inventors: Robert Mears, Hideki Takeuchi, Erwin Trautmann
  • Patent number: 9935011
    Abstract: A method includes forming Shallow Trench Isolation (STI) regions in a semiconductor substrate and a semiconductor strip between the STI regions. The method also include replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer has a first germanium percentage higher than a second germanium percentage of the second semiconductor layer. The method also includes recessing the STI regions to form semiconductor fins, forming a gate stack over a middle portion of the semiconductor fin, and forming gate spacers on sidewalls of the gate stack. The method further includes forming fin spacers on sidewalls of an end portion of the semiconductor fin, recessing the end portion of the semiconductor fin, and growing an epitaxial region over the end portion of the semiconductor fin.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Ting-Hung Hsu, Chao-Hsiung Wang, Chi-Wen Liu
  • Patent number: 9929154
    Abstract: A fin shaped structure and a method of forming the same. The method includes providing a substrate having a first fin structure and a second fin structure. Next, an insulation material layer is formed on the substrate. Then, a portion of the first fin structure is removed, to form a first recess. Following this, a first buffer layer and a first channel layer are formed sequentially in the first recess. Next, a portion of the second fin structure is removed, to form a second recess. Then, a second buffer layer and a second channel layer are formed in the second recess sequentially, wherein the second buffer layer is different from the first buffer layer.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: March 27, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Yin Weng, Cheng-Tung Huang, Wei-Heng Hsu, Yu-Ming Lin, Ya-Ru Yang
  • Patent number: 9911760
    Abstract: A thin film transistor substrate including a second electrode connected to a first electrode within a shared contact hole; and a fourth electrode connected to a third electrode within the shared contact hole, wherein the shared contact hole penetrates through a plurality of stacked insulating layers, and wherein an insulating layer below at least one of a connection portion in which the first electrode and the second electrode are connected and a connection portion in which the third electrode and the fourth electrode are connected has an undercut structure within the shared contact hole.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: March 6, 2018
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Kangil Kim, Haye Kim, Chansoo Park
  • Patent number: 9899349
    Abstract: Methods of forming a semiconductor package. Implementations include providing a leadframe, coupling a semiconductor die or an electronic component to the leadframe, and encapsulating at least a portion of the semiconductor die or the electronic component using a mold compound leaving two or more leads of the leadframe exposed. The method may also include coating the two or more leads of the leadframe with an electrically conductive layer. The method may include fully electrically and physically singulating one or more tie bars between two or more leads of the leadframe, a lead of the two or more leads and a leadframe flag or any combination thereof. The method may also include singulating the leadframe to form one or more semiconductor packages.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: February 20, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Phillip Celaya, James P Letterman, Jr., Robert L. Marquis, Darrell Truhitte
  • Patent number: 9899385
    Abstract: A semiconductor integrated circuit includes a protected circuit connected to two power supply lines that provide a supply voltage, a detecting circuit that includes a resistive element and a capacitive element connected in series between two power supply lines and detects a surge generated in the power supply line based on potential variation of an inter-element connecting node, and a protection transistor that is connected between two power supply lines and has a control electrode connected to an output of the detecting circuit. The protection transistor has the control electrode formed from a different electrode material having a work function difference from a transistor of the same channel conductivity type in the protected circuit, to have a different threshold voltage from the transistor so that the amount of leakage current per unit channel width may be smaller compared with the transistor.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: February 20, 2018
    Assignee: SONY CORPORATION
    Inventors: Takashi Yamazaki, Shimpei Tsujikawa
  • Patent number: 9871101
    Abstract: A semiconductor structure, and methods for forming the semiconductor device are provided. In various embodiments, the semiconductor device includes a substrate, source/drain regions over the substrate, a plurality of nanowires over the substrate and sandwiched by the source/drain regions, a gate dielectric layer surrounding the plurality of nanowires, and a gate layer surrounding the gate dielectric layer.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: January 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Gerben Doornbos, Chun-Hsiung Lin, Chien-Hsun Wang, Carlos H. Diaz
  • Patent number: 9837514
    Abstract: Various particular embodiments include an integrated circuit (IC) structure having: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region; and a collector contact region contacting the collector region under the intrinsic base and the collector-base region via the doped subcollector region.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: December 5, 2017
    Assignee: International Business Machines Corporation
    Inventors: Joseph R. Greco, Qizhi Liu, Aaron L. Vallett, Robert F. Vatter
  • Patent number: 9825080
    Abstract: A structure of insulation between photodiodes formed in a doped semiconductor layer of a first conductivity type extending on a doped semiconductor substrate of the second conductivity type, the insulating structure including a trench crossing the semiconductor layer, the trench walls being coated with an insulating layer, the trench being filled with a conductive material and being surrounded with a P-doped area, more heavily doped than the semiconductor layer.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: November 21, 2017
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Nayera Ahmed, François Roy
  • Patent number: 9812601
    Abstract: A device, system, and method for a multi junction solar cell are described herein. An exemplary multi-solar cell structure can have a substrate having a first surface having a (111) crystalline etched surface. A dielectric layer can be deposited on the first surface of the substrate. A graded buffer layer can be grown on a second surface of the substrate with the second surface having a (100) crystalline surface. A first solar subcell within or on top of the graded buffer layer and a second solar subcell grown on top of the first solar subcell.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: November 7, 2017
    Assignee: Amberwave Inc.
    Inventor: Anthony Lochtefeld
  • Patent number: 9799790
    Abstract: A method for preparing a mesoscopic solar cell based on perovskite light absorption materials, the method including 1) preparing a hole blocking layer on a conductive substrate; 2) preparing and sintering a mesoporous nanocrystalline layer, an insulation separating layer, and a hole collecting layer on the hole blocking layer in order; and 3) drop-coating a precursor solution on the hole collecting layer, and allowing the precursor solution to penetrate pores of the mesoporous nanocrystalline layer via the hole collecting layer from top to bottom, and drying a resulting product to obtain a mesoscopic solar cell.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: October 24, 2017
    Assignee: WONDER SOLAR LIMITED LIABILITY COMPANY
    Inventors: Hongwei Han, Zhiliang Ku
  • Patent number: 9780008
    Abstract: A method for manufacturing a semiconductor device including: a process of applying a sealing composition for a semiconductor to a semiconductor substrate, to form a sealing layer for a semiconductor on at least the bottom face and the side face of a recess portion of an interlayer insulating layer, the sealing composition including a polymer having a cationic functional group and a weight average molecular weight of from 2,000 to 1,000,000, each of the content of sodium and the content of potassium in the sealing composition being 10 ppb by mass or less on an elemental basis; and a process of subjecting a surface of the semiconductor substrate at a side at which the sealing layer has been formed to heat treatment of from 200° C. to 425° C., to remove at least a part of the sealing layer.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: October 3, 2017
    Assignee: MITSUI CHEMICALS, INC.
    Inventors: Shoko Ono, Yasuhisa Kayaba, Hirofumi Tanaka, Kazuo Kohmura, Tsuneji Suzuki
  • Patent number: 9780041
    Abstract: A method for making EMI shielding layer on a package is disclosed to include the steps of: a) disposing a UV curable adhesive which can be thermally released on a light-transmissive substrate; b) placing the package on the UV curable adhesive in such a way that the UV curable adhesive adheres to and cover a surface of the package having solder pads; c) irradiating UV light toward the light-transmissive substrate to cure the UV curable adhesive; d) forming an EMI shielding layer on the package; and e) thermally releasing the UV curable adhesive.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: October 3, 2017
    Assignee: Universal Scientific Industrial (Shanghai) Co., Ltd.
    Inventor: Pioneer Chien
  • Patent number: 9773822
    Abstract: The present application discloses an array substrate comprising a first layer comprising a data line; at least one second layer comprising at least one data line overlapping area on intersections between the first layer and the at least one second layer; and a spacer layer between the first layer and the second layer. The spacer layer comprises a plurality of spacer units spaced apart from each other. Each of the plurality of spacer units is in an area corresponding to the overlapping area.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: September 26, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Jun Ma
  • Patent number: 9768281
    Abstract: An object is to provide a semiconductor device including a semiconductor element which has favorable characteristics. A manufacturing method of the present invention includes the steps of: forming a first conductive layer which functions as a gate electrode over a substrate; forming a first insulating layer to cover the first conductive layer; forming a semiconductor layer over the first insulating layer so that part of the semiconductor layer overlaps with the first conductive layer; forming a second conductive layer to be electrically connected to the semiconductor layer; forming a second insulating layer to cover the semiconductor layer and the second conductive layer; forming a third conductive layer to be electrically connected to the second conductive layer; performing first heat treatment after forming the semiconductor layer and before forming the second insulating layer; and performing second heat treatment after forming the second insulating layer.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: September 19, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Ohara, Toshinari Sasaki
  • Patent number: 9741897
    Abstract: A method for fabrication a light emitting diode (LED) includes forming alternating material layers on an LED structure, formed on a substrate, to form a reflector on a back side opposite the substrate. A handle substrate is adhered to a stressor layer deposited on the reflector. The LED structure is separated from the substrate using a spalling process to expose a front side of the LED structure.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: August 22, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Devendra K. Sadana, Davood Shahrjerdi