Abstract: An embodiment is a device comprising a semiconductor die, an adhesive layer on a first side of the semiconductor die, and a molding compound surrounding the semiconductor die and the adhesive layer, wherein the molding compound is at a same level as the adhesive layer. The device further comprises a first post-passivation interconnect (PPI) electrically coupled to a second side of the semiconductor die, and a first connector electrically coupled to the first PPI, wherein the first connector is over and aligned to the molding compound.

Abstract: The disclosure relates to a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate; a nanowire structure protruding from the substrate comprising a channel region between a source region and a drain region; a pair of silicide regions extending into opposite sides of the source region, wherein each of the pair of silicide regions comprising a vertical portion adjacent to the source region and a horizontal portion adjacent to the substrate; and a metal gate surrounding a portion the channel region.

Abstract: According to one embodiment, provided is a polycrystallization method for polycrystallizing an amorphous semiconductor film that has a natural oxide film on the surface. The polycrystallization method includes a step of cleaning the natural oxide film while leaving the natural oxide film on the surface of the amorphous semiconductor film, and a step of polycrystallizing the amorphous semiconductor film in the state where the natural oxide film is left.

Abstract: A first metallic hard mask layer over an interconnect-level dielectric layer is patterned with a line pattern. At least one dielectric material layer, a second metallic hard mask layer, a first organic planarization layer (OPL), and a first photoresist are applied above the first metallic hard mask layer. A first via pattern is transferred from the first photoresist layer into the second metallic hard mask layer. A second OPL and a second photoresist are applied and patterned with a second via pattern, which is transferred into the second metallic hard mask layer. A first composite pattern of the first and second via patterns is transferred into the at least one dielectric material layer. A second composite pattern that limits the first composite pattern with the areas of the openings in the first metallic hard mask layer is transferred into the interconnect-level dielectric layer.

Abstract: A semiconductor structure comprising an improved ESD protection device is provided. The semiconductor structure comprises a substrate, a well formed in the substrate, a first heavily doped region formed in the well, a second heavily doped region formed in the well and separated apart from the first heavily doped region, a gate structure formed on the substrate between the first heavily doped region and the second heavily doped region, a field region formed in the well under the first heavily doped region and the gate structure, and a field oxide/shallow trench isolation structure formed adjacent to the first heavily doped region. The field region is not formed under the second heavily doped region. The well and the field region have a first type of doping. The first heavily doped region and the second heavily doped region have a second type of doping.

Abstract: Disclosed are methods and resulting structures which provide an opening for epitaxial growth, the opening having an associated projection for reducing the size of the contact area on a substrate at which growth begins. During growth, the epitaxial material grows vertically from the contact area and laterally over the projection. The projection provides a stress relaxation region for the lateral growth to reduce dislocation and stacking faults at the side edges of the grown epitaxial material.

Abstract: A gate structure is provided. The gate structure includes a substrate, a gate disposed on the substrate and a gate dielectric layer disposed between the substrate and the gate, wherein the gate dielectric layer is in the shape of a barbell. The barbell has a thin center connecting to two bulging ends. Part of the bulging ends extends into the gate and the substrate.

Abstract: A semiconductor device comprises first and second gate stacks formed on a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a dielectric layer interposed between a bulk substrate layer and an active semiconductor layer. A first extension implant portion is disposed adjacent to the first gate stack and a second extension implant portion is disposed adjacent to the second gate stack. A halo implant extends continuously about the trench. A butting implant extends between the trench and the dielectric layer. An epitaxial layer is formed at the exposed region such that the butting implant is interposed between the epitaxial layer and the dielectric layer.

Abstract: A method for fabricating a light emitting diode die includes the steps of providing a carrier substrate and forming an epitaxial structure on the carrier substrate including a first type semiconductor layer, a multiple quantum well (MQW) layer on the first type semiconductor layer configured to emit light, and a second type semiconductor layer on the multiple quantum well (MQW) layer. The method also includes the steps of forming a plurality of trenches through the epitaxial structure, forming a reflector layer on the second type semiconductor layer, forming a seed layer on the reflector layer and in the trenches, and forming a substrate on the seed layer having an area configured to protect the epitaxial structure.

Abstract: MIMCAP diodes are provided that can be suitable for memory device applications, such as current selector devices for cross point memory array. The MIMCAP diodes can have lower thermal budget as compared to Schottky diodes and controllable lower barrier height and lower series resistance as compared to MIMCAP tunneling diodes. The MIMCAP diode can include a barrier height modification layer, a low leakage dielectric layer and a high leakage dielectric layer. The layers can be sandwiched between two electrodes.

Abstract: The invention relates to a method for producing serially interconnected optoelectronic components as well as optoelectronic components interconnected according to the method. In a first step, an electrically non-conductive layer with optoelectronic material introduced therein and at least one first wire or thread (2) located in the layer is produced. The first wire or thread either is electrically conductive from the outset or can subsequently be treated in such a way that it becomes electrically conductive as a result of the treatment. A first and second electrooptically active region of the layer is electrically connected to the first wire or thread in such a way that they are electrically interconnected to each other in series. By the wire, regions of the layer are subdivided in a simple manner, as a result of which a plurality of optoelectronic components are produced in a technically simple manner. Continuous production is possible.

Abstract: A semiconductor device includes a fin-shaped semiconductor layer disposed on a semiconductor substrate, a first insulating film disposed around the fin-shaped semiconductor layer, a first pillar-shaped semiconductor layer disposed on the fin-shaped semiconductor layer, a first gate insulating film that is disposed around the first pillar-shaped semiconductor layer and includes a charge storing layer, a second gate insulating film disposed around the first pillar-shaped semiconductor layer and at a position higher than the first gate insulating film, a fifth gate insulating film surrounding an upper portion of the first pillar-shaped semiconductor layer, and a first contact electrode surrounding the fifth gate insulating film.

Abstract: An optical device including a substrate and a light emitting layer formed on the front surface of the substrate. Both the front surface and the back surface of the substrate are parallel to each other and have substantially the same rectangular shape. The substrate has four side surfaces connecting the front surface and the back surface of the substrate. Of the four side surfaces, each of the two side surfaces adjacent to each other has a convex sectional shape between the front surface and the back surface of the substrate, and each of the other two side surfaces adjacent to each other has a concave sectional shape between the front surface and the back surface of the substrate.

Abstract: A method of producing a patterned polymeric insulator includes providing a substrate. A patterned polymeric inhibitor is provided on the substrate. An inorganic thin film is deposited using an atomic layer deposition process on the substrate in an area where the patterned polymeric inhibitor is absent. A material layer is deposited over the inorganic thin film and the patterned polymeric inhibitor.

Abstract: Various particular embodiments include a method of amorphizing a portion of silicon underneath the N+ base section of a PNP transistor structure. After amorphizing, the method can include selectively etching that implant-amorphized silicon to trim the collector-base area and collector-base junction. The selective etching is enhanced because the unimplanted silicon region etches at a distinct rate than the implant-amorphized silicon, allowing for control over the trimming of the collector-base junction.

Abstract: Provided is a semiconductor device having improved performance. In a semiconductor substrate located in a memory cell region, a memory cell of a nonvolatile memory is formed while, in the semiconductor substrate located in a peripheral circuit region, a MISFET is formed. At this time, over the semiconductor substrate located in the memory cell region, a control gate electrode and a memory gate electrode each for the memory cell are formed first. Then, an insulating film is formed so as to cover the control gate electrode and the memory gate electrode. Subsequently, the upper surface of the insulating film is polished to be planarized. Thereafter, a conductive film for the gate electrode of the MISFET is formed and then patterned to form a gate electrode or a dummy gate electrode for the MISFET in the peripheral circuit region.

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device includes: a first conductive type semiconductor layer including a first lower conductive type semiconductor layer and a first upper conductive type semiconductor layer; a V-pit passing through at least one portion of the first upper conductive type semiconductor layer; a second conductive type semiconductor layer placed over the first conductive type semiconductor and filling the V-pit; and an active layer interposed between the first and second conductive type semiconductor layers with the V-pit passing through the active layer. The first upper conductive type semiconductor layer has a higher defect density than the first lower conductive type semiconductor layer and includes a V-pit generation layer comprising a starting point of the V-pit.

Abstract: The present invention provides a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate. The present invention further provides a method of making the same.

Abstract: This TFT substrate (100A) includes: a gate connecting layer (3a) formed on a substrate (1) out of a same conductive film as a gate electrode (3) or a transparent connecting layer (2a) formed on the substrate (1) out of a same conductive film as a first transparent electrode (2); an oxide layer (5z) which is formed on an insulating layer (4) and which includes at least one conductor region (5a); and a source connecting layer (6a) formed on the oxide layer (5z) out of a same conductor film as a source electrode (6s). The source connecting layer (6a) is electrically connected to either the gate connecting layer (3a) or the transparent connecting layer (2a) via the at least one conductor region (5a).

Abstract: A method for fabricating the phase change memory cells. The method includes forming an electrically conductive bottom electrode within a substrate. A heat shield is formed within the substrate and above the bottom electrode. The heat shield is thermally coupled to the bottom electrode, includes a sidewall and extends away from the bottom electrode. A heating element is formed within the sidewall of the heat shield. The heating element is electrically coupled to the bottom electrode and is configured to generate heat during programming of the phase change memory cell.