Abstract: An embodiment may be an apparatus comprising a link coupled with a memory, and circuitry coupled with the link to calculate the amount of memory access idle time, determine if memory access idle time is sufficient to change to a self-refresh state, and change to a self-refresh state based on memory access idle time without explicit notification from a processor regarding the processor power state. Another embodiment may be a method for memory to enter self-refresh comprising calculating the amount of memory access idle time, determining if memory access idle time is sufficient to change to a self-refresh state, and changing to a self-refresh state based on memory access idle time without explicit notification from a processor regarding the processor power state. Various other embodiments systems, methods, machine readable mediums and apparatuses may provide similar functionality to these exemplary embodiments.

Abstract: A processor module includes an execution unit and a power monitor for monitoring power consumption by processor components including said execution unit.

Abstract: A mobile computing device comprises a central processing unit (CPU), memory that communicates with said CPU, an interface that communicates with said memory and said CPU and a display that communicates with said interface. A first distributed load center has first and second load terminals and includes at least a first distributed load. A second distributed load center has first and second load terminals and includes at least a second distributed load. A first distributed power source includes a first battery that is directly connected and primarily supplies power to the first and second load terminals of the first distributed load center. A second distributed power source includes a second battery that is directly connected and primarily supplies power to the first and second load terminals of the second distributed load center.

Abstract: Disclosed are embodiments of a method, apparatus and system for a low power state for a point-to-point link. During the low power state, the signal on both conductors of a differential transmit pair are driven to electrical idle. Analog activity detectors are enabled during the low power state and are disabled during normal power state. Exit from the low power state does not require a physical layer re-initialization sequence. Other embodiments are also described and claimed.

Abstract: A method and apparatus are disclosed for power management of an electronic device. The present invention reduces power consumption of an electronic device that communicates over a network by selecting a transmission mode with reduced power consumption as the battery level gets lower. A disclosed power management process monitors the battery level of an electronic device and selects a transmission mode (e.g., a transmission rate) with a lower power consumption when the battery power level reaches one or more predefined threshold levels.

Abstract: A multiple security level power managed processing system and method of managing power consumption in a multi security level system is disclosed. The system includes a plurality of nodes having a processor, associated memory and a processor interface. A plurality of processors individually may include multiple independent processing security levels, such as a first processing level and a second processing level. A MILS processor-to-processor network connects the plurality of processors. The system may be configured to distribute the application among the processing levels corresponding to a specific level of security. Power management profiles are used to control operation of the processors to maximize power efficiency while meeting security criteria.

Abstract: Particular implementations are particularly useful in providing a system in which the hardware is more easily upgradable and new hardware functionality may be added without adding any new physical hardware. Through placement of an FPGA closely associated with the CPU of a personal computer, the FPGA may be reconfigured to act as new hardware. A system for installing new virtual hardware involves loading firmware into memory associated with the FPGA and reconfiguring the FPGA through a microcontroller. Particular implementations include universal ports associated with the FPGA into which adapter plugs can be placed to quickly adapt to any device that may be added through the virtual hardware use of the FPGA. Other implementations include high density connectors into which a plurality of ports of varying configurations may be plugged for connection of external electronic equipment through the FPGA.

Abstract: A semiconductor chip has: a plurality of hard macros which operates based on a reference clock; and a clock pad through which the reference clock is supplied from the outside to one of the plurality of hard macros. The reference clock supplied to the one hard macro is relayed to other hard macros of the plurality of hard macros in order.

Abstract: A card having a first device and a second device is plugged into a root port having a predefined root port width. The first device is trained and the device lane width is determined. If the root port width is greater than the device lane width then the root port is dynamically configured via hardware strapping to include a predefined number of adjacent ports with each port having a lane width equal to the device lane width. The root port is reset to force training of the first device and the second device.

Abstract: A processor comprises a software control module specifying a power performance metric. A policy manager is responsive to the software control module. A dispatch scheduler is responsive to the policy manager to operate the processor in accordance with the power performance metric.

Abstract: A power management system for a multiple compute component system. The management system enables operational management of individual compute components in two low power states of operation, suspend and hibernate. In addition, the management system enables granular management of power consuming accessories within an individual compute component. When a compute component is in the low power state of suspend or hibernate, it may be hot-swapped to a different locale. In addition, when a compute component is restored from a low power state of hibernate, it may access an alternate image in the system. Accordingly, the power management system allows for five state of operation of an individual component in a multiple compute component system.

Abstract: Circuits, methods, and apparatus for deskewing rising and falling edges of a clock signal. One embodiment of the present invention utilizes a delay element in a data path to adjust a data signal such that a clock signal is centered relative to the data. A further embodiment of the present invention recovers a double-data rate signal using two flip-flops, one clocked by clock rising edges, the other clocked by clock falling edges. An additional delay element is inserted in front of one or both flip-flop clock inputs. If two additional delay elements are used, they are independently adjustable such that each edge can be independently adjusted for improved data recovery.

Abstract: An over-heat protecting circuit and a system circuit board thereof are disclosed. The over-heat protecting circuit receives a voltage-detecting signal, a control signal, and an over-heat signal, and comprises a first logic circuit, a memory circuit, and a second logic circuit. The first logic circuit receives and processes the voltage-detecting signal and the over-heat signal to output a first logic signal. The memory circuit receives and processes the first logic signal and the control signal to output a latching signal. The second logic circuit receives and processes the latching signal and the control signal to output a power-control signal. Eventually, the power supplier stops outputting an operating voltage according to the power-control signal.

Abstract: A computer determines whether it has been booted from a hard disk drive or from an alternate source (e.g., a floppy drive or portable memory) that entails a higher risk of importing a virus into the computer, and if it is determined that a non-HDD source was booted from, corrective action such as a virus scan can be preemptively taken.

Abstract: An operation mode control program is a program for carrying out an operation mode changeover control. A user interface section sets time zone corresponding to each operation mode. A time acquire section periodically acquires system time from an internal clock section of an operating system, and transfers the system time to an operation mode changeover section. The operation mode changeover section carries out the operation mode changeover control in accordance with time zone set by the user interface section while receiving the system time from the time acquire section.

Abstract: When a rebuild process is to be performed for a disk array, a power supply is checked. In this case, when a battery is used, the rebuild process is inhibited in accordance with a user setting. The remaining capacity of the battery is checked to change the effective rate of the rebuild process on the basis of the remaining capacity. A consistency check is also performed in the same manner.

Abstract: A method and apparatus for adaptively adjusting the operating voltage of an integrated circuit in response to tester-to-system variations, worst-case testing techniques, process variations, temperature variations, or reliability wearout mechanisms. The minimum operating voltage of an integrated circuit is determined either during external testing of the integrated circuit or during built-in-self-testing. The minimum operating voltage is transmitted to a variable voltage regulator where it is used to set the output of the regulator. The output of the regulator supplies the integrated circuit with its operating voltage. This technique enables tailoring of the operating voltage of integrated circuits on a part-by-part basis which results in power consumption optimization by adapting operating voltage in response to tester-to-system variations, worst-case testing techniques, process variations, temperature variations or reliability wearout mechanisms.

Abstract: An information handling system hardware signature based on a verified hardware configuration for the information handling system serves as a reference to confirm the hardware configuration of the information handling system through a manufacture process. For instance, after hardware component testing, the hardware components of the information handling system are queried and compared against the hardware signature to ensure continued compliance with the verified configuration. Similarly, the hardware configuration is confirmed against the hardware signature after loading an image and prior to final test of the assembled information handling system. Comparison of current hardware with the hardware signature throughout the manufacture process ensures compliance with a predetermined hardware configuration without requiring multiple hardware verifications.

Abstract: A method and system for reducing power consumed by a computer system. A network switch includes a processor coupled to a plurality of ports which are coupled to a plurality of computer systems. The processor includes logic for receiving a media access control address from one of the computer systems. The computer system may later enter into either a hibernation state or an off state. The processor may further include logic for receiving a magic packet that includes a repetitive address that identifies the computer system. Upon receiving the magic packet, the processor remotely activates the computer system from either the hibernation state or the off state. By remotely activating the computer system, the computer system may consume less power since the network subsystem in the computer system may not need to monitor for a magic packet. Instead, the magic packet may be monitored by the network switch.

Abstract: To reduce power consumption of a processor system including a plurality of processors without degradation of the processing ability, a flag detecting section detects an assignment control flag and a clock control flag added to instruction code. An instruction assignment controlling section outputs the instruction code to a CPU or an HWE based on the detection to have the instruction code executed. A clock controlling section supplies a clock signal having a frequency lower than the maximum clock frequency to one of the CPU and the HWE in which a waiting time arises when the CPU and the HWE operate at the maximum clock frequencies, thus reducing power consumption.