Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension.

Abstract: A microcomputer device contains a CPU with an arithmetic/logic unit and data/address busses and registers on a single semiconductor integrated circuit having on-chip macrocode and microcode storage. A byte-wide macrocode word is fetched from the ROM and stored in an instruction register in the CPU, then multiple-byte-wide microcode words are fetched from microcode store based on this macrocode word. Also, the microcode can be accessed one byte at a time for processing through the ALU via the data/address busses and registers, as if the microcode was data.

Abstract: A data processing system including a central processing unit (CPU) having an operating system to process information, and a main memory coupled to the CPU to store information, wherein the CPU accesses the main memory by means of an actual address after translating an associative address into the actual address by means of the operating system. To that end, the CPU includes a dynamic address translator having a page table addressed by the associative address and outputting a portion of the actual address when being addressed by the associative address. A remaining portion of the actual address is derived from the associative address itself.

Abstract: A data processing system includes a microprogram controlled central processing unit that executes instructions. The instruction words include a data type field for identifying the type of operand processed during the execution of the instruction. The data type field signals and a number of control signals are applied to the address terminals of a read only memory. The read only memory output signals are tested by microwords of a microprogram to branch to firmware routines to process the operand type.

Abstract: A closed-loop magnetic roll/yaw control system for high inclination satellites where the predominant component of the geomagnetic field lies in the orbit plane of the satellite. The system includes a torquing means that forms a magnetic dipole moment parallel to the pitch axis. The torquing means is energized to minimize roll or yaw error only in two spaced portions 1 and 3 of its orbit. Each of the portions lie between the extension of the earth's magnetic equatorial plane and a second plane normal to the orbit and passing through the magnetic poles of the earth. Portions 1 and 3 are those parts of the orbit in which the satellite is traveling toward the second plane. The torquing means is de-energized after the satellite crosses the second plane and is in either of the remaining spaced portions 2 and 4 of its orbit.

Abstract: A data processing system includes a host unit and terminal equipment connected thereto. Different terminal equipment is identified on the basis of a program provided on the side of the host unit and on the basis of data transaction with the hardware of the terminals. To this end, a microprogram is transferred from the host computer to the terminals, while the result of execution of the microprogram determined on the basis of the types of the terminals and components thereof is transferred to the host computer from the terminal. In this way, confidential security is assured between the host and the terminals.

Abstract: In a method of controlling a multicomputer system which includes a plurality of computers connected to a common transfer bus, each of the plurality of computers decides whether or not the adjacent computer is abnormal, and the computer which has decided that the adjacent computer is abnormal cuts off this adjacent computer from the transfer bus.

Abstract: A virtual storage data processing system having an address translation unit shared by a plurality of processors, located in a memory control unit connected to a main memory is disclosed. One of the plurality of processors is a job processor which accesses the main memory with a virtual address to execute an instruction and includes a cache memory which is accessed with a virtual address. One of the plurality of processors is a file processor which accesses the main memory with a virtual address to transfer data between the main memory and an external memory. The cache memory receives the virtual address when the file processor writes to the main memory and if it contains a data block corresponding to the virtual address, it invalidates the corresponding data block. The address translation unit translates the address differently for the access from the file processor and the accesses from other processors.

Abstract: A method of operating a computer system is disclosed that is useful in connection with programs that provide the user with messages such as error messages. The error messages are stored in an indexed file, at least some of the messages having token words whose meaning must be provided in order to give complete meaning to the error message. A dictionary list of the definitions for all token words that may be encountered when a command of the program is executed is developed prior to a point in the program where a message is retrieved from the indexed file. If the proper condition is developed to indicate that an error message is necessary, the error message number corresponding to that condition is used to recover the appropriate error message with token words either from the indexed file or from a local header table. The token words are then replaced with definitions from the dictionary list and the error message is delivered to the user.

Abstract: The cycle time of a data processing system should always be determined in such a manner that data from a source register, after having been propagated through, if necessary, several transfer sections and line drivers, and through a chain of logic circuits for the respective processing steps, can be stored in the result or sink register safely and even with the worst case propagation tolerance of all elements involved. The ideal cycle time therefore, which is dependent on the processing speed of the slowest chain of logic circuits, has to have added time segments for the worst case of unprecise clocking.A reduction of the cycle time by the above mentioned added time segments, and if necessary by the propagation delays in the transfer sections and in the line drivers, is achieved when the chain of logic circuits and thus its delay time is divided into two partial chains with the partial delays and if the sink register is arranged between the two partial chains.

Abstract: Programmable controllers are connected in a ring by serial data links. Each controller periodically transmits information packets on the ring which contain its I/O image table data. All controllers on the ring receive such data and store it in their data tables, and such data is thus available for examination by each controller processor during its execution of the user's control program.

Abstract: A method and apparatus predicting the outcome of a conditional branch instruction based on the previous performance of the branch, rather than on the instruction fields. The prediction of the outcome of a conditional branch instruction is performed utilizing a table that records the history of the outcome of the branch at a given memory location. A decode-time history table (DHT) is utilized. The DHT attempts to guess only the outcome of a conditional branch instruction, but not its target address. Thus, it can only be used to guess the branch outcomes at decode time when the target address is available. During the decoding of a conditional branch instruction, a table is accessed using the memory address of the branch instruction itself or some portions thereof. The table records the history of the outcomes of the branch at this memory location up to the congruence of the table size. A combinational circuit determines the guess (taken or not taken) from the branch history as provided by the table.

Abstract: A data proessing system includes a processor, a memory, a direct memory accessing (DMA) control unit and an input/output adapter. A memory area of a given capacity is reserved in the memory for storing control information transferred between the processor and the adapter. For transfer of the control information, the adapter accesses the control information stored in the memory area through direct memory accessing under control of the DMA control unit while the processor can make access to the control information through a memory read/write command. By storing at the predetermined area of the memory the control information transferred between the processor and the adapter, the quantity of hardware and the number of IC's required for implementing the adapter can be significantly reduced. Conflicting access requests to the main memory area by the processor and adapter are prevented through time-division control of the memory bus.

Abstract: A microcomputer processor comprises a scratch-pad storage, an arithmetic-logical unit, an interface unit and a microprogram unit, all interconnected by means of an intraprocessor data bus, and a processor status register. The processor further comprises a constant file, first and second switching elements connected to the arithmetic-logical unit, a register, a source of logic potentials and a decoder. The present invention helps increase the speed of microcomputer processor and expand its functional capabilities.

Abstract: An information processing unit, such as a central processor, microprocessor or one-chip microcomputer, which can be used as either a master unit or a slave unit yet does not require the provision of extra external terminals for control signals. The unit is provided with first and second bidirectional input/output ports and an internal bus coupled to both of the first and second input/output ports. The input/output mode of the two busses can be controlled either by an internally-generated control signal or by an externally-supplied control signal inputted to the unit. The one of the first and second control signals used for controlling the transmission modes of the input/output ports is determined in accordance with data input through one of the input/output ports and stored internally of the unit.

Abstract: A method for detection of a sequential data stream which can be performed without host computer intervention is disclosed featuring examination of a data record and channel program during read operations for signals indicative that the data is not part of a sequential data stream, for example, embedded seek instructions. If a particular sought for record does not contain such indications, the successive record or records may then be staged to a faster access memory device such as a solid-state cache. The invention is described in a plug-compatible, software-transparent configuration.

Abstract: Picture information stored in a memory device is read out and written into a page buffer and visually displayed on the screen of a CRT display under control of an interface unit for display, through a size conversion circuit.

Abstract: An address converting and generating system for an information processing system is disclosed. The address converting and generating system includes a segment type memory and an instruction having an operation code part, a field for specifying a register for loading a physical address representing a segment relative address, and a displacement for specifying a logical address. This instruction is decoded by an instruction decoder, and the physical address is generated from the logical address by referring to a segment table directory and a segment table. The generated physical address is loaded, together with a segment base address, a segment table number, and a segment table entry, in a register specified by the register specifying field. An effective address is generated by addition of the contents of the specified register and the address specified by the displacement. The system further has an instruction for generating a logical address from a physical address.

Abstract: A storage hierarchy has a backing store and a caching buffer store. During a series of accesses to the hierarchy by a user, writing data to the hierarchy results in data being selectively removed from the buffer store. Space in said buffer store not being allocated to data being written results in such data being written to the backing store to the exclusion of the buffer store. Removal of data increases the probability of writing data to the backing store. In a preferred implementation, the backing store is one or more disk type data storage apparatus and the buffer store is an electronic random access memory.

Abstract: A priority sorting system for sorting information on a priority basis is disclosed having at least first, second, third and fourth data stores arranged horizontally so that the input of one data store is connected to the output of the preceding data store, and a plurality of comparators, each comparator connected to a pair of data stores with no data store being connected to more than one comparator, said comparators swapping information stored in said data stores on a priority basis.