Abstract: An electronic translator is disclosed wherein a first word or words represented in a first language are entered to obtain a second word or words represented in a second language equivalent to the first word or words. The translator comprises an input circuit for entering the first word or words, a memory circuit for storing the second word or words, an access circuit for addressing the memory to cause retrieval of the second word or words, a retrieval control circuit for selecting the retrieval speed of the access means and an indicating circuit responsive to the access circuit for indicating the second word or words.

Abstract: A system for transmitting digital information including a coding arrangement, a transfer medium, for example a record carrier, and a decoding arrangement.In the coding arrangement the digital information is received as groups of input words which are encoded to form code words, each code word corresponding to an input word. Each code word has a time duration equal to s.tau..sub.O and each is assembled from M subgroups G.sub.m of I signal positions t.sub.mi spaced by equal time intervals .tau., where m is a number from 1 to M, inclusive, corresponding to a subgroup G.sub.m and i is a number within each subgroup G.sub.m from 1 to I inclusive. In each subgroup G.sub.m, k of these signal positions t.sub.mi are always occupied by a signal which is distinguishable from the signal in unoccupied positions, where k is an integer smaller than I (1.ltoreq.k.ltoreq.I-1). The first positions of the subgroups G.sub.m are located at mutually different time intervals .epsilon..sub.

Abstract: An improvement is provided to a text processor having an interactive display terminal. The improvement provides for a combination of said text processor with a data processor and means for conducting data processing sessions utilizing the data processor between text processing sessions carried out by said text processor. During such data processing sessions, the interactive display terminal of said text processor emulates a data processing terminal. The emulated display terminal is connected to the data processor whereby the emulated terminal functions as a display terminal for the data processor. Further, means are provided which are operational during the data processing session to define the outer dimensions of a limited area on the display terminal to correspond to the dimensions of the data processing display terminal screen being emulated.

Abstract: A job processing method is provided for use in an information processing system including three or more information processing devices connected to a common transmission line:(a) first of all, in case the occurrence of a job is detected at one of the three or more processing devices, it is broadcast to the remaining plural processing devices;(b) next, that job execution for that job is started at a first processing device which is one of the plural processing devices receiving the job occurrence broadcast or the processing device having broadcast the job occurrence;(c) then, the first processing device having started that job execution is monitored at the others of the plural processing devices which are not presently involved in that job execution but have been informed of that job occurrence; and(d) the job is executed irrespective of the presence of an abnormal processing device in case a second processing device, which is one of the plural monitoring processing devices, detects an abnormality of the proce

Abstract: In a programmable machine, a combination for executing a do loop without requiring "overhead" steps to be included in the do loop, having means for determining when the final do loop step is being executed, means for counting the number of do loop iterations remaining, and means for proceeding to the first do loop step each time the final do loop step is being executed provided the last iteration has not been reached, or otherwise for exiting from the do loop.

Abstract: An information processing system is disclosed which includes a display, a memory, a keyboard and a control unit. The system may store and display data in a table format by record and field. The system may be employed in an entry edit mode whereby data is entered or edited by an operator through the keyboard into the system. The system may also operate in a record selection mode whereby data in a field having a predetermined relation to a field value may be selected by the system. The system permits the entry of comparison operators and field values below the field heading in the display for the field to be searched. The keys representing the comparison operators and the keys representing data are at separate locations on the keyboard to prevent operator error in input. This feature is particularly advantageous when one symbol may be employed both as a comparison operator and data. Such a symbol would then be represented by two keys on the keyboard.

Abstract: Operation of a computer system after a main memory failure is enabled by storing a read-only access shadow copy of its data structures in another memory having an independent failure mode. The shadow copy is periodically updated at a series of checkpoints. Where the data structure is a linked list, updating without recopying is enabled by prelinking the list item in the read-only list to the beginning of a second read/write list, which is appended to the first list at the next checkpoint.

Abstract: A display word processor (11) has the capability of emulating a data processing terminal for a host data processor (10) in an information processing system. With such a capability, the display word processor may be switched between data processing and word or text processing sessions. In this information processing system, the interactive display (17) is operable during data processing sessions to display a word processing message when a word processing task is being carried out as a background task during the data processing session. The word processing message may be displayed on a message line (7) which may be shared with a data processing message. Alternatively, if the interactive display terminal (17') is large enough, the word processing message line (9) may be displayed in an area dedicated to the word processing message.

Abstract: The disclosure relates to an improvement to an information processing system for conducting data processing operations wherein the processing relates to the value of the information and conducting text processing operations wherein the processing affects only the format of information. The improvement provides the combination of means for initiating a data processing session in said system, means for switching to a text processing session before the completion of the data processing session, means for storing the status of the non-completed data processing session during the text processing session, and means for switching back from the text processing session to the non-completed data processing session.

Abstract: A system for use in an electronic digital signal processor for assembling multiple report definition instructions to create a shell document to generate a file report. The system enables an operator to depress an instruction key to call up an instruction menu and select for display the report definition instruction menu. The operator chooses report instructions desired in any order, and the system inserts chosen instructions in proper order to build the shell document. The operator keys report information in between the instructions. The shell document is stored in machine-dependent language to enable the document to be redisplayed in operator-dependent language as determined by the current program loaded in the processor.

Abstract: An information processing apparatus includes a RAM for storing character information and character pitch information corresponding thereto; a CRT for simultaneously displaying character information having different character pitches; line buffers supplied with the information from the RAM; a character pitch switching circuit for producing a character pitch or load clock signal in response to the character pitch information stored in the RAM; a memory address counter for reading out the contents of the line buffers at a rate determined by the character pitch clock signal; an address setting circuit for producing an address signal for a horizontal scroll operation in which the displayed characters are shifted in the horizontal direction on the screen; start address registers for determining how many characters to shift in response to the address signal and in accordance with the character pitch with which each is associated; and a selecting circuit for gating the output from only one of the start address regist

Abstract: A system and method for distribution of articles or services, especially adapted to be secure against use by unauthorized personel, receives first and second data carriers. Each data carrier includes a processor, data storage, and interfacing circuits. A random number generator feeds a random number to each of the data carriers which use a program to generate a resultant based on the random number, a secret code and an identification number. The secret code and identification number are stored in the data storage of each data carrier. The resultants are compared to determine if they are equal, in which case access is allowed.

Abstract: A control unit for a functional processor is disclosed which minimizes programming complexity by eliminating data transfers and the transfer control associated with two level memory systems and which improves flexibility in program task changeovers in pipelined arithmetic architectures. This is accomplished by employing common page addressing for accessing memory address stacks for storing either main memory addresses or address increments, coefficient address stacks for storing coefficient memory addresses or address increments, and microinstruction sequencing control branch stacks for storing branch and loop control parameters. This permits chaining of long sequences of signal processing subroutines without external control and the associated execution time overhead.

Abstract: A graphic display system uses a plurality of identical processor units each of which is controlled by microcode to perform a particular function in transforming, clipping, and scaling geometric data for presentation on a display. Each processor includes a plurality of function units which can operate independently, in parallel, or in master-slave mode. Each function unit comprises a plurality of one bit slice circuits which can be fabricated using VLSI techniques. Each one bit slice includes a multilevel memory which collectively provide a dispersed stack for the function unit.

Abstract: In a data processing system having a memory and employing N-bit bytes and two byte addresses, a branch instruction which can cross one page boundary is executed without having to use calculations to effect a change in the contents of the program counter (PC). It is determined whether the value V1 of the (N-1) least significant bits (LSB's ) of the lower order byte of the two byte branch address is greater or less than the value V2 of the (N-1) least significant bits (LSB's) of the lower order byte of the address to which the PC is pointing and also whether PC N.noteq.BR N where PC N and BR N are the most significant bits of the lower order bytes of the PC address and the branch address, respectively. If V1<V2, PC N=1, and PC N.noteq.BR N, the upper order byte of the PC address is incremented by 1 and if V1>V2, PC N=0, and PC N.noteq.BR 7, the upper order byte of the PC address is decremented by 1.

Abstract: A method for use in an electronic digital signal processing system for improving execution time in locating requested programs, reducing program storage requirements in memory and improving packaging and repackaging of programs on direct access memory devices for the library. A program data set for a system is formed to recognize the references to character program names and to resolve those references into control section identification codes. Each referenced character program name is uniquely encoded to a 16 bit control section identification code used as an input to a table lookup routine. The encoded control section identification for the program library loaded on the direct access memory consists of a data set number, a module index number and a control section number. A similar data structure is used to locate programs in storage by program management once they have been retrieved from the program library stored on a direct access memory device of the system.

Abstract: A processor module is one of several modules mounted in a rack to form a programmable controller. The module has a microprocessor that executes a sequence of machine language instructions to interpret and thereby execute macroinstructions that are part of a control program stored in a read/write volatile main memory. The rate of execution is improved by reducing the instructions in a fetch sequence used in coupling each macroinstruction to its interpreter sequence of machine-language instructions. Hardware assistance is provided to allow expansion of macroinstruction operation codes as they are fetched. The processor module also allows the user to program his own interpreter sequences for specially defined macroinstructions and to load these sequences into a nonvolatile memory that is plugged into the module. An external auxiliary power supply is connected to the processor module to supply the programming voltage required by the nonvolatile memory.

Abstract: There is described a unique apparatus for exchanging commands and data via a dedicated memory which has ports connected to the data and address busses of two different microprocessors. The system operates even though the microprocessors have different word lengths, e.g. a sixteen bit processor and an eight bit processor. The system permits interfacing between the microprocessors with different bit size words and allows each of the microprocessors to treat the exchange memory as part of its own memory space without locking one microprocessor off of a shared bus.

Abstract: A data communications system for asynchronous communication having at least two data transmit/receive terminals wherein the display is periodically updated with new send or receive data. In the receive mode the data is accumulated in a receive buffer for a predetermined time interval and then transferred into a text storage buffer which then activates a display access method to process the stored data and update the display. The display access method then goes into an "idle" mode and waits for the next transfer of data which does not occur until the predetermined time interval has expired. In the transmit mode the send data is transmitted without a delay but the display is updated after the predetermined time interval has expired.

Abstract: Apparatus that discourages the use of computer equipment with software that is not approved for such use by the manufacturer of the computer equipment. This apparatus requires software to generate display producing signals but to produce them for a short enough period of time to be imperceptible. The display may be the identification of a patent or patent application.