Abstract: A computer-controlled system, such as an elevator, is tested by augmenting computer operation with a diagnostic device containing a computer and coded diagnostic programs that a service technician identifies through a keyboard using diagnostic test codes that appear on an overlay which contains special codes and identifiers associated with numerical displays and lights on the diagnostic device for correlating test results to the test performed according to the program.

Abstract: Self-test techniques for checking driver circuits connected to a bus are described that particularly involve the detection and isolation of failures in off-chip-drivers and connections.

Abstract: A memory redundancy circuit is described incorporating a sequential row or column counter associated with a plurality of programmable row or column decoders. The sequential row counter includes a sequence circuit for each programmable row decoder. The sequence circuit and programmable row decoder incorporate fixed and variable threshold transistors such as metal nitride oxide semiconductor (MNOS) transistors. The threshold of the variable threshold transistors are switched in response to address signals and control signals to permit redundancy. A disable circuit is also described to permit removal of the redundancy circuits to permit retest of the other circuits.

Abstract: In a data transmission device having at least one transmitting station and at least one receiving station the same message is transmitted with an integer number of copies. This number may vary from one message to another. The number is predetermined by the transmitting station as a function of the reliability of the network and the functional importance of the message; thus, the same sequencing of the general events is presented to all stations without any acknowledge process being required.

Abstract: A data retransmitting system in which data is transmitted in data frames having a predetermined length and an answer signal is transmitted back from the signal receiving side upon reception of each data frame. A measuring frame is transmitted from the signal transmitting side prior to the start of data transmission. A transmission delay time is measured from a time difference between transmission of the measuring frame and reception of an answer signal to said measuring frame from the signal receiving side according to the transmission delay time, a frame length for each data frame and a monitoring time which elapses the time instant that each frame has been transmitted until the corresponding answer signal is detected. When, with respect to each data frame having the frame length thus determined, no answer signal is detected within said monitoring time thus determined the data is retransmitted.

Abstract: In a stored program controlled electronic telephone switching system transmission links are provided from a host office, provided with a central processor, to one or more remote offices, each provided with a remote processor. Data and control information are continually passed between the host office and each remote office in a digital time-division format. Data integrity is monitored through a cyclic odd and even patterned parity scheme which predetermines the parity of sequential time slots in one direction of transmission and reflects that parity pattern in the return direction of transmission between host office and remote offices. The patterned parity scheme detects hardware faults in the interface for the transmission links between host and remote offices on a continuous basis.

Abstract: Circuitry for a fault-tolerant computer is disclosed which circuitry is constructed in two identical halves. Each half, by itself, is not a functionally-complete circuit, however, the two identical halves can be connected together to provide a functionally-complete circuit. Each of the two circuit halves is considerably less complex than a functionally-complete circuit yet, when connected together, the two halves provide fault detection capabilities equivalent to a computer system in which the outputs of two functionally-complete, redundant circuits are compared to detect faults.In particular, each inventive circuit half contains a complete data processing and control unit but only one half of the memory which is necessary for a functionally-complete unit. The processing units on each circuit half operate simultaneously on identical data and the same address information is provided to the memories on each circuit half.

Abstract: A description is given of a system for communication between a transmitting station (30) and a receiving station (33) by way of a message which consists of a direct succession of a number of identical code words. Each message uses only a comparatively small part of the capacity of the message channel. Each code word has at least a predetermined minimum Hamming distance with respect to any other code word, including the cyclic transpositions of the latter code word. Therefore, for the detection and reproduction of a code word it is not necessary to realize word synchronization and a given category of errors can still be detected and/or corrected. The code words may concern, for example, a transmitter or program identification in a broadcasting system or a paging code for a receiving station in a system comprising selectively addressable receiving stations as in a paging system.

Abstract: A method and apparatus for instruction parity error recovery in a programmable data processor wherein the instruction parity error is logged for future reference, the instruction causing the error is reloaded to memory and the program is restarted at the point of error. This method for "soft" recovery from an instruction parity error forces a No-Operation instruction onto the processor's instruction bus in place of the faulty instruction when a parity error is detected during instruction fetch, stores the address of the instruction having the parity error, and forces the next instruction to the processor from a parity error recovery routine. The parity error recovery routine logs the error, restores the instruction from local disk storage or from a remote host system in communication with the programmable data processor and forces the processor to resume fetching instructions at the address where the error occurred.

Abstract: The subject parity circuit generates a single parity bit for a prescribed DATA SET. The DATA SET comprises n bytes which are simultaneously transmitted to the parity circuit over n data transmission leads. The n bytes are simultaneously combined bit by bit to determine whether an odd or even number of bits have been received. A cummulative sum is determined, and the single parity bit is generated with the receipt of the last n bits of the DATA SET.

Abstract: An apparatus for diagnosing a plurality of digital-to-analog converters simultaneously is provided. Digital signal generation means applies digital signals to the plurality of digital-to-analog converters, and the digital signals are changed in sequence so that the analog outputs from the converters are changed symmetrically with respect to a first predetermined value. The analog outputs from the converters are combined by a resistor network, and the combined output is compared with a second predetermined value by a comparator. If the comparator's output is kept to a predetermined level regardless of changing the digital signals, the digital-to-analog converters are judged that they operate properly.

Abstract: In a similar-redundant signal system employing two or more channels, the signals in the different channels below a predetermined frequency are equalized, the equalization preferably being performed digitally. The equalization reduces the slight differences between signals in the different channels in the absence of channel failure, and thus enables the thresholds for channel failure detection by comparison of the signals in different channels to be reduced.

Abstract: A memory checking circuit for periodically reading the data from all locations therein. The circuit includes logic to correct and restore data from locations where an error has occurred. The circuit quickly identifies all memory locations present during search mode at a fast rate and reads all present locations at a slower rate during normal mode.

Abstract: The present invention is a video casette recorder (hereinafter referred to as "VCR") backup controller that can be installed in a S-100 bus system which is compatible with NTSC, PAL and SECAM systems. The controller provides temporary storage and control capability for the S100 interface bus system. The controller organizes the data into data blocks and synchronizes the data to TV signals during the write mode. The control further replicates data for error detection in the read and write modes.

Abstract: An improved dynamic memory system including through-checking and error detection of the refresh counter is described. A refresh counter that provides parity of the refresh count for through-checking, of refresh addresses is shown. Error detecting circuitry is utilized in conjunction with the refresh counter and the parity generating circuitry to detect errors in functionality of the refresh counter. The refresh counter is a Gray code counter constructed of a double rank of latches operable with code generating logic circuits for determining the sequence of generation of Gray code groupings.

Abstract: A circuit test system using signature analysis allows random probing to detect faults in an assembly under test. Test points on a properly working assembly are probed at random and the signatures obtained are listed in a memory or storage media. Thereafter, when testing other boards these same test points are probed randomly and the signatures are compared to the list of possible good signatures. If a match is found a "pass" indication is generated and the operator tests another node. If a match is not found, a "failure" indication is generated and more detailed troubleshooting of circuits at that test node commences.

Abstract: A process control system includes redundant digital controllers and a plurality of input/output (I/O) modules for interfacing with remote field sensors and actuators. Bi-directional communication between controllers and I/O modules is achieved by a parallel-wired, process I/O bus. Failures within the system, including the bus structure itself, that continually keep the bus active (i.e., in a low state) are isolated by a combination of software diagnostic routines for performing bus checkout and a unique quick disconnect feature that readily isolates the fault condition first between the I/O module nest area and the controllers, then, if necessary, to individual I/O modules. During fault isolation procedures, individual I/O modules may be disconnected from the bus while the values of field signals are simultaneously maintained to provide minimum process upset.

Abstract: In a magnetic disc device, track bytes are added to a record which is to be stored in a cylinder of a magnetic disc in order to utilize additional magnetic disc devices of a different type in the same manner as the first-mentioned magnetic disc device. The magnetic disc device provides track byte check device which checks track bytes read from the record for errors, stores the track bytes in a track byte register when they are correct, and, if the stored track bytes are re-read, utilizes the correct contents stored in the track byte register as the track bytes of the record.

Abstract: An improved error indicating system utilizing adder circuits for use with an error correction code system capable of detecting and indicating multiple bit errors and detecting and correcting single bit errors is described. The system utilizes an encoding system for generating a plurality of check bits, each check bit associated with a predetermined bit grouping of data bits within a data word. When a data word is accessed, read check bits are reconstituted from the read data and are compared to the check bits originally encoded. Syndrome bits are generated from the originally encoded check bits and the reconstituted read check bits, the syndrome bits thus generated, serving to identify whether the data word accessed contains no errors, a single bit error, or a multiple bit error. Decoder circuitry for decoding the syndrome bits and effecting the control signals for controlling the correction of single bit errors is described.

Abstract: A method for verifying the architectural integrity of a newly written or modified instruction set in a limited operating environment is described. More particularly, this methodology is adapted to perform such verification even though the processor under test has only a one or a few instructions in its partially complete instruction set. Such verification is accomplished using a minimum test driver, under control of a test processor, which loads the data necessary to execute the instruction being tested. The test system also provides actual or simulated I/O capabilities. After execution of that instruction, the test driver directs capture of the execution results for appropriate use. As an aid in performing the verification test, the test driver is provided with an invalid command that forces return of control to the test processor.