Abstract: An address and data bus connects a multiplicity of ports into which test modules can be inserted with a microcomputer controlled by a keyboard for performing tests on circuit boards or other electronic units through test plugs that are interconnected with the data ports where the test modules are plugged in. When the test system is put into operation, all of the ports of the data bus are addressed to produce an indication of which ports are occupied by test modules as well as of the nature of the test modules. When it is desired to produce a test, each step of the procedure is performed by operation of a keyboard with reference to available options presented on the computer display on the basis of the configuration of test modules that have been plugged in. Coupling fields are interposed between data ports designed to receive test modules utilizing analog circuits and a test connector for connection to equipment under test.

Abstract: The interface circuit is intended to be connected between a module terminal and a module itself and provides means for stimulating and sensing signals between the module and its terminal. The interface circuit comprises a decoupling section which connects or disconnects the interface circuit from the module, a test data section for receiving test data from outside sources, an inside section which connects the test data section with the interior of the module and an outside section which connects it with the terminal. A monitor section is also included to allow a terminal to be monitored while it is connected to from its module. The control section requires only four connections and generates the various control signals necessary to control the operation of the interface circuit.

Abstract: A parity checking arrangement for tag information in a cache memory. Parity generation is performed on the input tag in parallel with tag memory lookup and then compared with the parity stored in tag memory in order to speed operation. A single parity generator also may be used for writing into tag memory.

Abstract: Testing apparatus monitors signals at selected test points in a tested device. An operator specifies sets of signals defining a display window during which all signals at the selected test points will be available to the operator for immediate or later examination. One set of signals defines the beginning of the window. Another set defines the end of the window, but only after other sets or conditions, also specified by the operator, occur. For each set, the operator specifies test points monitored, signal states expected and what happens when the expected states occur.

Abstract: In a stand-alone or add-on sorter for a reproduction machine, the sorter has access to its own collection of diagnostic programs under control of a single push button carried on the sorter housing. A lamp associated with the push button is used to indicate, as by its frequency of pulsing, the diagnostic state of the machine, and a manually-operable switch is used to move the sorter between its normal and diagnostic modes. When in its stand-alone configuration, the number of successive sorting operations to be carried out by the sorter, before returning to its home position, is controlled by the number of successive operations of the push button, with the switch being in its normal position.

Abstract: An address bus of a central processor unit (CPU) is tested by generating repetitive "no operation" (NO OP) instructions. A microprocessor in the CPU receives the NO OP instruction code set manually into switches and generates sequential addresses on successive CPU cycles on the address bus. The microprocessor generates a read signal during each CPU cycle which is jumpered to portions of the logic to allow continuity of operation during test.

Abstract: A high speed code processing system for error correcting code is disclosed. It uses bit parallel residue generation for cyclic codes. This minimizes the time delay for cyclic code processing. Residue generation of the bit string is accomplished by processing multiple bits in each clock time instead of the conventional bit-by-bit implementation. Thus, the checkword calculation and the syndrome calculation are accomplished at a significantly higher speed than the conventional shift register approach to provide a system capable of on-line residue generation.

Abstract: In addition to a main memory device a spare memory device is provided. Both memory devices utilize word wires in common which are arranged to constitute matrix circuits together with groups of bit lines. When a bit error is contained in data read out from the main memory device, a correction circuit correcting the error and a register for storing the error are provided. An output of the register is used to switch a bit line from which the error has been detected to a corresponding bit line of the spare memory device.

Abstract: A high-speed, high-resolution testing circuit for both analog and digital circuit packs is described. The testing circuit, which employs data compression techniques, comprises a shift register (22) having an overall length selectively variable under program control, and an arrangement (18) for combining incoming data signals with feedback signals out of predetermined stages of the shift register. The positions of the feedback taps of the variable length shift register are selectively variable under program control (24,26).