Patents Examined by Mark V. Prenty
  • Semiconductor light detection element
    Patent number: 10529772
    Abstract: A semiconductor photodetector includes a semiconductor substrate including a silicon substrate. The semiconductor substrate includes a second main surface as a light incident surface and a first main surface opposing the second main surface. In the semiconductor substrate, carriers are generated in response to incident light. A plurality of protrusions is formed on the second main surface. The protrusion includes a slope inclined with respect to a thickness direction of the semiconductor substrate. At the protrusion, a (111) surface of the semiconductor substrate is exposed as the slope. The height of the protrusion is equal to or more than 200 nm.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: January 7, 2020
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Tatsuki Kasuya, Takeshi Kawahara, Yasuhito Miyazaki, Kentaro Maeta, Hisanori Suzuki
  • Semiconductor device with reduced flicker noise
    Patent number: 10529818
    Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a source region and a drain region arranged in a semiconductor substrate, where the source region is laterally separated from the drain region. A gate stack is arranged over the semiconductor substrate and between the source region and the drain region. A cap layer is arranged over the gate stack, where a bottom surface of the cap layer contacts a top surface of the gate stack. Sidewall spacers are arranged along sides of the gate stack and the cap layer. A resist protective oxide (RPO) layer is disposed over the cap layer, where the RPO layer extends along sides of the sidewalls spacers to the semiconductor substrate. A contact etch stop layer is arranged over the RPO layer, the source region, and the drain region.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Li Cheng, Liang-Tai Kuo, Yu-Chi Chang
  • Method for fabricating semiconductor device having buried metal line
    Patent number: 10522459
    Abstract: A method includes etching a semiconductor substrate to form a fin. An isolation structure is formed over the semiconductor substrate and around the fin. The isolation structure and the semiconductor substrate are etched to form a recess. A barrier layer is deposited over a bottom surface and a sidewall of the recess. A conductive layer is deposited over the barrier layer. The conductive layer is recessed to form a conductive line, in which a top surface of the conductive line is lower than a top surface of the isolation structure. A dielectric cap layer is formed over the conductive line. The isolation structure and the dielectric cap layer are recessed, such that the fin protrudes from the recessed isolation structure.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tetsu Ohtou, Yusuke Oniki, Hidehiro Fujiwara
  • Semiconductor device layout
    Patent number: 10522528
    Abstract: Semiconductor devices and semiconductor cell arrays are provided herein. In some examples, a semiconductor device includes a multi-fin active region, a mono-fin active region, and an isolation feature between the multi-fin active region and the mono-fin active region. The multi-fin active region includes a first plurality of fins, a second plurality of fins parallel to the first plurality of fins, a first n-type field effect transistor (FET), and a first p-type FET. The mono-fin active region abuts the multi-fin active region. The mono-fin active region includes a first fin, a second fin different from the first fin, a second n-type FET, and a second p-type FET. The isolation feature is parallel to the first and second gate structures.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon Jhy Liaw
  • Field-effect transistor and method therefor
    Patent number: 10522677
    Abstract: A transistor includes a trench formed in a semiconductor substrate with the trench having a first sidewall and a second sidewall. A vertical field plate is formed in the trench and the vertical field plate is located between the first sidewall and the second sidewall. A gate electrode is formed in the trench with a first edge of the gate electrode proximate to the first sidewall and a second edge of the gate electrode proximate to the vertical field plate. A first dielectric material is formed in the trench between the first sidewall and the vertical field plate. A second dielectric material is formed in the trench between the vertical field plate and the second sidewall with the second dielectric material having a dielectric constant lower than that of the first dielectric material.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: December 31, 2019
    Assignee: NXP USA, INC.
    Inventors: Saumitra Raj Mehrotra, Ljubo Radic, Bernhard Grote
  • Semiconductor device and method for fabricating the same
    Patent number: 10515976
    Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure; a first gate dielectric layer and a first gate electrode. The isolation structure is formed in the semiconductor substrate to divide the semiconductor substrate at least into a first active region and a second active region. The first gate dielectric layer is disposed on the first active region, and has a plane top surface contacting to a sidewall of the isolation structure and forming an acute angle therewith. The first gate electrode stacked on the plane top surface.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: December 24, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Chung Chang, Tzu-Ping Chen
  • Semiconductor structure including isolations and method for manufacturing the same
    Patent number: 10515845
    Abstract: A method for manufacturing a semiconductor structure including isolations includes receiving a substrate including a first region and a second region; forming a patterned hard mask, the patterned hard mask including a first opening exposing a portion of the first region and a second opening exposing a portion of the second region; removing portions of the substrate to form a first trench in the first region and to form a second trench in the second region; performing an ion implantation to a portion of the patterned hard mask in the first region and a portion of the substrate exposed from the first trench; enlarging the first opening to form a third opening over the first trench and enlarging the second opening to form a fourth opening over the second trench; and forming a first isolation by filling the first trench and a second isolation by filling the second trench.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wen-Shun Lo, Yu-Chi Chang, Felix Ying-Kit Tsui
  • Method for forming stressor, semiconductor device having stressor, and method for forming the same
    Patent number: 10516050
    Abstract: A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor including one material selected from the group consisting of He, Ne, and Ga.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: December 24, 2019
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Che-Wei Yang, Hao-Hsiung Lin, Samuel C. Pan
  • Memory cell having resistance variable film and method of making the same
    Patent number: 10516107
    Abstract: A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second electrode has a side surface. A portion of the side surface of the first electrode and a portion of the side surface of the second electrode sandwich a portion of the resistance variable film.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Pei Hsieh, Chia-Shiung Tsai, Chern-Yow Hsu, Fu-Ting Sung, Shih-Chang Liu
  • Packaging structures for metallic bonding based opto-electronic device and manufacturing methods thereof
    Patent number: 10510683
    Abstract: The present disclosure proposes a packaging structure for a metallic bonding based opto-electronic device and a manufacturing method thereof. According to the embodiments, the packaging structure for an opto-electronic device may comprise an opto-electronic chip and a packaging base. The opto-electronic chip comprises: a substrate having a first substrate surface and a second substrate surface opposite to each other; an opto-electronic device formed on the substrate; and electrodes for the opto-electronic device which are formed on the first substrate surface. The packaging base has a first base surface and a second base surface opposite to each other, and comprises conductive channels extending from the first base surface to the second base surface.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: December 17, 2019
    Assignees: Tsinghua University, NUCTECH COMPANY LIMITED
    Inventors: Wenjian Zhang, Qingjun Zhang, Yuanjing Li, Zhiqiang Chen, Ziran Zhao, Yinong Liu, Yaohong Liu, Xiang Zou, Huishao He, Shuwei Li, Nan Bai
  • Method to improve HKMG contact resistance
    Patent number: 10510858
    Abstract: A semiconductor device includes a substrate, a gate structure having a metal gate on the substrate, and a contact member extending into the metal gate. The contact member includes a first region on the metal gate and a second region on the first region. The first region has a cross-sectional size larger than a cross-sectional size of the second region. The semiconductor device has a reduced contact resistance between the contact member and the metal gate.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: December 17, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Lin Chen, Qiang Lei
  • Semiconductor device and method for fabricating the same
    Patent number: 10510609
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure; forming a mask layer on the first fin-shaped structure; and performing a first anneal process so that the first fin-shaped structure and the second fin-shaped structure comprise different radius of curvature.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: December 17, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Jen Chen, Tien-I Wu, Yu-Shu Lin
  • Integrated circuit and manufacturing method thereof
    Patent number: 10510753
    Abstract: An integrated circuit includes first and second semiconductor fins, first and second epitaxy structures, and first and second dielectric fin sidewall structures. The first and second epitaxy structures are respectively on the first and second semiconductor fins. The first epitaxy structure and the second epitaxy structure are merged together. The first and second dielectric fin sidewall structures are respectively on opposite first and second sidewalls of the first epitaxy structure. The first sidewall of the first epitaxy structure faces the second epitaxy structure. The first dielectric fin sidewall structure is shorter than the second dielectric fin sidewall structure.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jing Lee, Kun-Mu Li, Ming-Hua Yu, Tsz-Mei Kwok
  • Light-emitting element, light-emitting device, display device, electronic device, and lighting device
    Patent number: 10505135
    Abstract: An object is to provide a light-emitting element which uses a plurality of kinds of light-emitting dopants and has high emission efficiency. In one embodiment of the present invention, a light-emitting device, a light-emitting module, a light-emitting display device, an electronic device, and a lighting device each having reduced power consumption by using the above light-emitting element are provided. Attention is paid to Förster mechanism, which is one of mechanisms of intermolecular energy transfer. Efficient energy transfer by Förster mechanism is achieved by making an emission wavelength of a molecule which donates energy overlap with the longest-wavelength-side local maximum peak of a graph obtained by multiplying an absorption spectrum of a molecule which receives energy by a wavelength raised to the fourth power.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: December 10, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Seo, Shunpei Yamazaki, Takahiro Ishisone
  • Self-aligned source/drain contact for vertical field effect transistor
    Patent number: 10505048
    Abstract: A method for manufacturing a semiconductor device includes forming a fin on a semiconductor substrate. In the method, a bottom source/drain region is formed between the fin and the semiconductor substrate, and a top source/drain region is formed on the fin. The method further includes forming a cap layer covering part of a top surface of the top source/drain region. A portion of the top source/drain region and an underlying portion of the fin not covered by the cap layer are removed. The removal exposes a portion of the bottom source/drain region. A dielectric spacer is formed on a side of the fin adjacent the exposed portion of the bottom source/drain region, and extends onto a side of the top source/drain region. A bottom source/drain contact is formed on the exposed portion of the bottom source/drain region and on the dielectric spacer.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: December 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: Wenyu Xu, Chen Zhang, Kangguo Cheng, Xin Miao
  • Magnetoresistive effect element
    Patent number: 10505105
    Abstract: A magnetoresistive effect element includes: a first ferromagnetic layer as a magnetization fixed layer; a second ferromagnetic layer as a magnetization free layer; and a nonmagnetic spacer layer provided between the first ferromagnetic layer and the second ferromagnetic layer. The nonmagnetic spacer layer includes a nonmagnetic metal layer formed of Ag, and at least one of a first nonmagnetic insertion layer provided on a lower surface of the nonmagnetic metal layer and a second nonmagnetic insertion layer provided on an upper surface of the nonmagnetic metal layer. The first nonmagnetic insertion layer and the second nonmagnetic insertion layer include an Ag alloy, and thereby lattice mismatch between the nonmagnetic spacer layer, and the first ferromagnetic layer and/or the second ferromagnetic layer is reduced, compared to lattice mismatch when the entire nonmagnetic spacer layer is formed of Ag.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: December 10, 2019
    Assignee: TDK CORPORATION
    Inventors: Kazuumi Inubushi, Katsuyuki Nakada
  • Semiconductor device and method for fabricating the same
    Patent number: 10504992
    Abstract: There is provided a semiconductor device capable of enhancing short channel effect by forming a carbon-containing semiconductor pattern in a source/drain region. The semiconductor device includes a first gate electrode and a second gate electrode spaced apart from each other on a fin-type pattern, a recess formed in the fin-type pattern between the first gate electrode and the second gate electrode, and a semiconductor pattern including a lower semiconductor film formed along a profile of the recess and an upper semiconductor film on the lower semiconductor film, wherein the lower semiconductor film includes a lower epitaxial layer and an upper epitaxial layer sequentially formed on the fin-type pattern, and a carbon concentration of the upper epitaxial layer is greater than a carbon concentration of the lower epitaxial layer.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: December 10, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seok Hoon Kim, Hyun Jung Lee, Kyung Hee Kim, Sun Jung Kim, Jin Bum Kim, Il Gyou Shin, Seung Hun Lee, Cho Eun Lee, Dong Suk Shin
  • Low-capacitance electro-static-discharge (ESD) protection structure with two floating wells
    Patent number: 10504886
    Abstract: An Electro-Static-Discharge (ESD) input-protection device has an NPNP structure of a N+ cathode formed in a FINFET fin or highly-doped region over a floating P-well, and a P+ fin or highly-doped region anode formed over a floating N-well that touches the floating P-well. The floating P-well is surrounded by an isolating N-well and has a deep N-well underneath to completely isolate the floating P-well from the p-type substrate. No well taps are formed in the floating wells or in the isolating N-wells. The floating P-well and the floating N-well are thus truly floating at all times. Since the wells are floating, the NPNP structure appears as three junction diodes in series, which has a lower capacitance than a single diode that the NPNP structure would appear as when one of the wells was shorted or biased. During an ESD event the NPNP structure behaves as a single diode.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: December 10, 2019
    Assignee: Hong Kong Applied Science and Technology Research Institute Company, Limited
    Inventors: Chun-Kit Yam, Chenyue Ma, Shuli Pan
  • Buried word line structure and method of making the same
    Patent number: 10497704
    Abstract: A method of fabricating a buried word line structure includes providing a substrate with a word line trench therein. Two source/drain doped regions are disposed in the substrate at two sides of the word line trench. Later, a silicon oxide layer is formed to cover the word line trench. A titanium nitride layer is formed to cover the silicon oxide layer. Next, a tilt ion implantation process is performed to implant silicon atoms into the titanium nitride layer to transform part of the titanium nitride layer into a titanium silicon nitride layer. A conductive layer is formed in the word line trench. Subsequently, part of the conductive layer, part of the titanium silicon nitride layer and part of the silicon oxide layer are removed to form a recess. Finally, a cap layer fills in the recess.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: December 3, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Ger-Pin Lin, Kuan-Chun Lin, Chi-Mao Hsu, Shu-Yen Chan, Shih-Fang Tzou, Tsuo-Wen Lu, Tien-Chen Chan, Feng-Yi Chang, Shih-Kuei Yen, Fu-Che Lee
  • Semiconductor device and manufacturing method thereof
    Patent number: 10490496
    Abstract: This invention is to improve a performance of a semiconductor device. The semiconductor device includes a semiconductor substrate, a p-type well region formed in the semiconductor substrate, a first insulating layer formed over the p-type well region, a semiconductor layer formed over the first insulating layer, a second insulating layer formed over the semiconductor layer, and a conductor layer formed over the second insulating layer. A first capacitive element is comprised of the semiconductor layer, the second insulating layer, and the conductor layer, while a second capacitive element is comprised of the p-type well region, the first insulating layer, and the semiconductor layer, in which each of the semiconductor substrate and the semiconductor layer includes a single crystal silicon layer.
    Type: Grant
    Filed: February 24, 2018
    Date of Patent: November 26, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kawashima, Takashi Hashimoto