Abstract: A semiconductor device includes a source region, a drain region, a core channel region, and a barrier layer. The core channel region is between the source region and the drain region. The barrier layer is between the core channel region and the drain region. The barrier layer is a graded doped barrier layer.

Abstract: A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second electrode has a side surface. A portion of the side surface of the first electrode and a portion of the side surface of the second electrode sandwich a portion of the resistance variable film.

Abstract: The object of the present invention is to provide a nonvolatile storage element capable of suppressing retention degradation. A nonvolatile storage element is provided with a semiconductor substrate and a floating gate provided above the semiconductor substrate, in which the floating gate has an area of 30 ?m2 or more.

Abstract: A magnetoresistance structure includes a base that includes a conductive layer and a first active element on and in direct contact with the conductive layer. The magnetoresistance structure also includes a pillar structure connected to the base. The pillar structure includes a first hard mask, a capping material, a second active element and a tunnel layer. The magnetoresistance structure also further includes an etching barrier deposited on the pillar and the base; a second hard mask deposited on the etching barrier; and a capping barrier deposited on the second hard mask and covering side walls of the base.

Abstract: A device includes a fin structure protruding over a substrate, wherein the fin structure comprises a plurality of portions formed of different materials, a first carbon doped layer formed between two adjacent portions of the plurality of portions, a second carbon doped layer formed underlying a first source/drain region and a third carbon doped layer formed underlying a second source/drain region.

Abstract: A semiconductor structure and a method of forming the same are provided. In the semiconductor structure, contact spacers are formed at least on sidewalls of contact trenches in the substrate, so that the distance between the gate and the silicide layers disposed only on the bottom surfaces, rather than on the sidewalls and the bottom surfaces, of the contact trenches can be increased, and thus the current leakage induced by gate can be decreased.

Abstract: Techniques for VFET gate length control are provided. In one aspect, a method of forming a VFET device includes: patterning fins in a substrate; forming first polymer spacers alongside opposite sidewalls of the fins; forming second polymer spacers offset from the fins by the first polymer spacers; removing the first polymer spacers selective to the second polymer spacers; reflowing the second polymer spacers to close a gap to the fins; forming a cladding layer above the second polymer spacers; removing the second polymer spacers; forming gates along opposite sidewalls of the fins exposed in between the bottom spacers and the cladding layer, wherein the gates have a gate length Lg set by removal of the second polymer spacers; forming top spacers above the cladding layer; and forming top source and drains above the top spacers. A VFET device is also provided.

Abstract: This invention is to improve a performance of a semiconductor device. The semiconductor device includes a semiconductor substrate, a p-type well region formed in the semiconductor substrate, a first insulating layer formed over the p-type well region, a semiconductor layer formed over the first insulating layer, a second insulating layer formed over the semiconductor layer, and a conductor layer formed over the second insulating layer. A first capacitive element is comprised of the semiconductor layer, the second insulating layer, and the conductor layer, while a second capacitive element is comprised of the p-type well region, the first insulating layer, and the semiconductor layer, in which each of the semiconductor substrate and the semiconductor layer includes a single crystal silicon layer.

Abstract: A magnetoresistive effect element, which includes: a first ferromagnetic layer as a magnetization fixed layer; a second ferromagnetic layer as a magnetization free layer; and a nonmagnetic spacer layer provided between the first ferromagnetic layer and the second ferromagnetic layer. The nonmagnetic spacer layer includes an Ag alloy represented by General Formula (1), and thereby lattice mismatch between the nonmagnetic spacer layer, and the first ferromagnetic layer and/or the second ferromagnetic layer is reduced, compared to lattice mismatch when the nonmagnetic spacer layer is formed of Ag, Ag?X1-???(1) where X indicates one element selected from the group made of Al, Cu, Ga, Ge, As, Y, La, Sm, Yb, and Pt, and 0<?<1.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a source region and a drain region arranged in a semiconductor substrate, where the source region is laterally separated from the drain region. A gate stack is arranged over the semiconductor substrate and between the source region and the drain region. A cap layer is arranged over the gate stack, where a bottom surface of the cap layer contacts a top surface of the gate stack. Sidewall spacers are arranged along sides of the gate stack and the cap layer. A resist protective oxide (RPO) layer is disposed over the cap layer, where the RPO layer extends along sides of the sidewalls spacers to the semiconductor substrate. A contact etch stop layer is arranged over the RPO layer, the source region, and the drain region.

Abstract: A semiconductor structure includes a substrate having a first region and a second region defined thereon, a first isolation in the first region, a second isolation in the second region, and a region surrounding the first isolation in the substrate. The substrate includes a first material, and the region includes the first material and a second material. The first isolation has a first width, the second isolation has a second width, and the first width is greater than the second width. A bottom and sidewalls of the first isolation are in contact with the region, and a bottom and sidewalls of the second isolation are in contact with the substrate.

Abstract: A method for manufacturing a semiconductor device includes forming a fin on a semiconductor substrate. In the method, a bottom source/drain region is formed between the fin and the semiconductor substrate, and a top source/drain region is formed on the fin. The method further includes forming a cap layer covering part of a top surface of the top source/drain region. A portion of the top source/drain region and an underlying portion of the fin not covered by the cap layer are removed. The removal exposes a portion of the bottom source/drain region. A dielectric spacer is formed on a side of the fin adjacent the exposed portion of the bottom source/drain region, and extends onto a side of the top source/drain region. A bottom source/drain contact is formed on the exposed portion of the bottom source/drain region and on the dielectric spacer.

Abstract: A method for fabricating semiconductor device includes: forming a fin-shaped structure on a substrate, wherein the fin-shaped structure is extending along a first direction; forming a gate layer on the fin-shaped structure; removing part of the gate layer and part of the fin-shaped structure to form a first trench for dividing the fin-shaped structure into a first portion and a second portion, wherein the first trench is extending along a second direction; forming a patterned mask on the gate layer and into the first trench; removing part of the gate layer and part of the fin-shaped structure to form a second trench, wherein the second trench is extending along the first direction; and filling a dielectric layer in the first trench and the second trench.

Abstract: A magnetic memory including a plurality of magnetoresistance effect elements that hold information, each including a first ferromagnetic metal layer with a fixed magnetization direction, a second ferromagnetic metal layer with a varying magnetization direction, and a non-magnetic layer sandwiched between the first and second ferromagnetic metal layers; a plurality of first control elements that control reading of the information, wherein each of the plurality of first ferromagnetic metal layers is connected to a first control element; a plurality of spin-orbit torque wiring lines that extend in a second direction intersecting with a first direction which is a stacking direction of the magnetoresistance effect elements, wherein each of the second ferromagnetic metal layers is joined to one spin-orbit torque wiring line; a plurality of second control elements that control electric current flowing through the spin-orbit torque wiring lines.

Abstract: A magnetoresistive effect element includes a first ferromagnetic layer, a second ferromagnetic layer, a nonmagnetic layer, and at least one of a first nonmagnetic insertion layer provided directly on a lower surface of the nonmagnetic layer and a second nonmagnetic insertion layer provided directly on an upper surface of the nonmagnetic layer. The first nonmagnetic insertion layer and the second nonmagnetic insertion layer include an Ag alloy represented by General Formula (1): Ag?X1-? where X indicates one element selected from the group consisting of Al, Cu, Ga, Ge, As, Y, La, Sm, Yb, and Pt, and 0<?<1.

Abstract: Light emitting devices and methods for their manufacture are provided. According to one aspect, a light emitting device is provided that comprises a substrate having a recess, and an interlayer dielectric layer located on the substrate. The interlayer dielectric layer may have a first hole and a second hole, the first hole opening over the recess of the substrate. The light emitting device may further include first and second micro LEDs, the first micro LED having a thickness greater than the second micro LED. The first micro LED and the second micro LED may be placed in the first hole and the second hole, respectively.

Abstract: A semiconductor photodetector includes a semiconductor substrate including a silicon substrate. The semiconductor substrate includes a second main surface as a light incident surface and a first main surface opposing the second main surface. In the semiconductor substrate, carriers are generated in response to incident light. A plurality of protrusions is formed on the second main surface. The protrusion includes a slope inclined with respect to a thickness direction of the semiconductor substrate. At the protrusion, a (111) surface of the semiconductor substrate is exposed as the slope. The height of the protrusion is equal to or more than 200 nm.

Abstract: Disclosed is an illustrative bit cell that includes a first inverter circuit that includes a first input node and a first output node and a second inverter circuit that includes a second input node and a second output node, wherein the first output node is coupled to the second input node and the second output node is coupled to the first input node. The bit cell also includes a first extension field effect transistor that includes a first gate structure, a first cell-internal S/D region and a first cell boundary node S/D region, wherein first cell-internal S/D region electrically terminates within the cell boundary. The first gate structure is electrically coupled to one of the first or second input nodes and it is also shorted to the first cell-internal S/D region.

Abstract: A physical quantity sensor includes a substrate, an acceleration sensor mounted on the substrate, an integrated circuit mounted on the substrate and stacked with the acceleration sensor, and serial communication wirings provided to the substrate. In a plan view of the acceleration sensor element, a bonding wire connecting the acceleration sensor element to the integrated circuit is disposed on an opposite side to the serial communication wirings with respect to a virtual central line of the acceleration sensor element.

Abstract: A memory cell comprising a threshold switching material over a first electrode on a substrate. The memory cell includes a second electrode over the threshold switching material and at least one dielectric material between the threshold switching material and at least one of the first electrode and the second electrode. A memory material overlies the second electrode. The dielectric material may directly contact the threshold switching material and each of the first electrode and the second electrode. Memory cells including only one dielectric material between the threshold switching material and an electrode are disclosed. A memory device including the memory cells and methods of forming the memory cells are also described.