Abstract: A semiconductor optical device includes an element structure layer that includes a mesa stripe extending in a first direction; an electrode film that covers at least an upper surface of the mesa stripe; an electrode pad portion that covers a part of a first region positioned in a second direction, intersecting the first direction, relative to the mesa stripe on an upper surface of the element structure layer and is electrically connected to the electrode film; a first dummy electrode that covers another part of the first region and is electrically insulated from the electrode film; and a second dummy electrode that covers at least a part of a second region positioned in a third direction, opposite to the second direction, relative to the mesa stripe on the upper surface of the element structure layer and is electrically insulated from the electrode film, wherein the first dummy electrode includes a first portion disposed in the first direction relative to the electrode pad portion and a second portion dispose

Abstract: The present disclosure provides a semiconductor device which includes a base layer and a buffer structure. The base layer includes a first semiconductor compound having a first lattice constant and including a plurality of elements, and an atomic radius of one of the plurality of elements which has the largest atomic radius is defined as a first atomic radius. The buffer structure includes a second semiconductor compound and a first additive. The second semiconductor compound has a second lattice constant and the first additive has a second atomic radius. The second lattice constant is larger than the first lattice constant, and the second atomic radius is larger than the first atomic radius.

Abstract: Some embodiments include a method of forming an arrangement. A first tier is formed to include CMOS circuitry. A second tier is formed to include an assembly which has first and second sets of memory cells on opposing sides of a coupling region. A support material is adjacent the first and second sets of the memory cells, and an intervening material is adjacent the support material. The support material has a different composition than the intervening material. A conductive interconnect extends through the intervening material. An upper surface of the assembly is polished to reduce an overall height of the assembly. The support material provides support during the polishing to protect the memory cells from being eroded during the polishing. The conductive interconnect of the second tier is coupled with the CMOS circuitry of the first tier. Some embodiments include multitier arrangements.

Abstract: The present invention provides a white light LED package structure and a white light source system, which includes a substrate, an LED chip, and a wavelength conversion material layer. The peak emission wavelength of the LED chip is between 400 nm and 425 nm; the peak emission wavelength of the wavelength conversion material layer is between 440 nm and 700 nm, and the wavelength conversion material layer absorbs light emitted from the LED chip and emits a white light source; and the emission spectrum of the white light source is set as P(?), the emission spectrum of a blackbody radiation having the same color temperature as the white light source is S(?), P(?max) is the maximum light intensity within 380-780 nm, S(?max) is the maximum light intensity of the blackbody radiation within 380-780 nm, D(?) is a difference between the spectrum of the white light LED and the spectrum of the blackbody radiation, and within 510-610 nm, the white light source satisfies: D(?)=P(?)/P(?max)?S(W)/S(?max), ?0.

Abstract: The present disclosure relates to a light emitting diode. The light emitting diode comprises a first semiconductor layer, a second semiconductor layer, an active layer, a first electrode, and a second electrode. The active layer is located between the first semiconductor layer and the second semiconductor layer. The first electrode is a first carbon nanotube, the second electrode is a second carbon nanotube. A first extending direction of the first carbon nanotube and a second extending direction of the second carbon nanotube are crossed with each other. A vertical p-n junction or a vertical p-i-n junction is formed by the first semiconductor layer and the second semiconductor layer in a direction perpendicular to the first semiconductor layer.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a dielectric layer over a semiconductor substrate and forming a conductive line in the dielectric layer. The method also includes forming an etch stop layer over the dielectric layer and the conductive line and patterning the etch stop layer to form a contact opening exposing a portion of the conductive line. The method further includes forming a resistive layer over the etch stop layer, wherein the resistive layer extends into the contact opening. In addition, the method includes patterning the resistive layer to form a resistive element.

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

Abstract: A display panel includes a substrate, a transistor on the substrate, a storage capacitor on the substrate and electrically connected to the transistor, a metal layer between the substrate and the transistor, a first insulating layer on the metal layer and having a first contact hole, and a wiring connected to the metal layer through the first contact hole, wherein the first insulating layer having a first hole apart from the transistor.

Abstract: A light-emitting element includes: a base member including a first side and a second side, the first side and the second side being along a first direction, wherein a second direction from the first side toward the second side is orthogonal to the first direction; a semiconductor stacked body that is not electrically connected to the base member in a third direction, the third direction being orthogonal to a plane including the first direction and the second direction, the semiconductor stacked body comprising a p-type semiconductor layer, a light-emitting layer, and an n-type semiconductor layer; a first pad electrode that is not electrically connected to the base member in the third direction; a second pad electrode that is not electrically connected to the base member in the third direction; a first conductive layer; and a second conductive layer.

Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.

Abstract: A microelectromechanical systems (MEMS) package with roughness for high quality anti-stiction is provided. A device substrate is arranged over a support device. The device substrate comprises a movable element with a lower surface that is rough and that is arranged within a cavity. A dielectric layer is arranged between the support device and the device substrate. The dielectric layer laterally encloses the cavity. An anti-stiction layer lines the lower surface of the movable element. A method for manufacturing the MEMS package is also provided.

Abstract: A circuit package is provided, the circuit package including: an electronic circuit; a metal block next to the electronic circuit; encapsulation material between the electronic circuit and the metal block; a first metal layer structure electrically contacted to at least one first contact on a first side of the electronic circuit; a second metal layer structure electrically contacted to at least one second contact on a second side of the electronic circuit, wherein the second side is opposite to the first side; wherein the metal block is electrically contacted to the first metal layer structure and to the second metal layer structure by means of an electrically conductive medium; and wherein the electrically conductive medium includes a material different from the material of the first and second metal layer structures or has a material structure different from the material of the first and second metal layer structures.

Abstract: Techniques for forming RRAM cells with increased density are provided. In one aspect, a method of forming a RRAM device includes: providing an underlayer disposed on a substrate; patterning trenches in the underlayer; forming bottom electrodes at two different levels of the underlayer that includes first bottom electrodes at bottoms of the trenches and second bottom electrodes along a top surface of the underlayer in between the trenches; depositing an insulating layer on the first/second bottom electrodes; and forming top electrodes on the insulating layer, wherein the top electrodes include word lines, wherein the first and second bottom electrodes include bit lines that are orthogonal to the word lines. A RRAM device is also provided.

Abstract: Under one aspect, a non-volatile nanotube diode device includes first and second terminals; a semiconductor element including a cathode and an anode, and capable of forming a conductive pathway between the cathode and anode in response to electrical stimulus applied to the first conductive terminal; and a nanotube switching element including a nanotube fabric article in electrical communication with the semiconductive element, the nanotube fabric article disposed between and capable of forming a conductive pathway between the semiconductor element and the second terminal, wherein electrical stimuli on the first and second terminals causes a plurality of logic states.

Abstract: An ultraviolet light-emitting diode is disclosed. The ultraviolet light-emitting diode includes a transparent substrate, an ultraviolet illuminant epitaxial structure, and a transparent structure. The transparent substrate includes a first surface and a second surface which are opposite to each other, and a plurality of side surfaces surrounding and disposed between the first surface and the second surface. The ultraviolet illuminant epitaxial structure is disposed on the first surface of the transparent substrate. The transparent structure has a light-entering surface and a light-exiting surface which are opposite to each other. The light-entering surface of the transparent structure is adjacent to the second surface of the transparent substrate, and a refractive index of the transparent structure is between a refractive index of the transparent substrate and a refractive index of air.

Abstract: A silicon carbide semiconductor substrate includes an epitaxial layer. A difference of a donor concentration and an acceptor concentration of the epitaxial layer is within a range from 1×1014/cm3 to 1×1015/cm3. Further, the donor concentration and the acceptor concentration of the epitaxial layer are a concentration unaffected by an impurity inside epitaxial growth equipment.

Abstract: A light emitting diode having multiple tunnel junctions is provided. This comprises the common contact layer, the first and second tunnel junction layers respectively disposed on the bottom surface and the upper surface of the common contact layer, the first light emitting structure disposed on the bottom surface of the first tunnel junction layer and the second light emitting structure disposed on the upper surface of the second tunnel junction layer. Light emitting structures emitting blue and green light may be disposed above and below the common contact layer. By injecting holes into the first light emitting structure and the second light emitting structure through the common contact layer formed of the n-type semiconductor, current spreading effect is improved, leading to improved light emitting efficiency. Since the n-type semiconductor layer can be disposed on the upper surface exposed to the outside, risk of damage occurring in subsequent fabrication steps can be reduced.

Abstract: A strained relaxed silicon germanium alloy buffer layer is employed in the present application to induce a tensile stain on each suspended semiconductor channel material nanosheet within a nanosheet material stack that is present in a long channel device region of a semiconductor substrate. The induced tensile strain keeps the suspended semiconductor channel material nanosheets that are present in long channel device region essentially straight in a lateral direction. Hence, reducing and even eliminating the sagging effect that can be caused by surface tension.

Abstract: A device structure for a bipolar junction transistor includes a base layer made of a semiconductor material. An emitter is disposed on a first portion of the base layer. A dopant-containing layer is disposed on a second portion of the base layer. A hardmask is disposed on the base layer. The hardmask includes a window aligned with the second portion of the base layer. Deposits of the dopant-containing layer are limited to exposed surfaces of: the first portion that is disposed on a top surface of the base layer inside of the window.

Abstract: A semiconductor device includes stack structures each including a first conductive layer, a substrate disposed under the stack structures, first impurity regions disposed in the substrate, and at least one trench passing through the stack structures and disposed above the first impurity regions.