Abstract: A nitride-based light-emitting diode (LED) device includes an n-type nitride semiconductor layer, an active layer that is disposed on the n-type nitride semiconductor layer, a p-type nitride semiconductor layer disposed on the active layer, and a defect control unit disposed between the n-type nitride semiconductor layer and the active layer. The defect control unit includes first, second and third defect control layers that are sequentially disposed on the n-type nitride semiconductor layer in such order, and that have different doping concentrations. The third defect control layer includes one of Al-containing ternary nitride, Al-containing quaternary nitride, and a combination thereof.

Abstract: A structure and a formation method of hybrid semiconductor devices are provided. The structure includes a substrate and a fin structure over the substrate. The fin structure has a channel height. The structure also includes a stack of nanostructures over the substrate. The channel height is greater than a lateral distance between the fin structure and the stack of the nanostructures. The structure further includes a gate stack over the nanostructures. The nanostructures are separated from each other by portions of the gate stack.

Abstract: The flip-chip light emitting diode structure includes a substrate, a first patterned current blocking layer, a second patterned current blocking layer, a first semiconductor layer, an active layer and a second semiconductor layer. The first patterned current blocking layer is disposed on the substrate. The second patterned current blocking layer is disposed on the first patterned current blocking layer, in which the first patterned current blocking layer and the second patterned current blocking layer are located on different planes, and patterns of the first patterned current blocking layer and patterns of the second current blocking layer are substantially complementary. The first semiconductor layer is disposed on the second patterned current blocking layer. The active layer is disposed on the first semiconductor layer. The second semiconductor layer is disposed on the active layer, in which electrical properties of the second semiconductor layer and the first semiconductor layer are different.

Abstract: A mold chase for packaging a compartmentally shielded multifunctional semiconductor is provided. The mold chase generally includes a first cavity and a second cavity separated by a trench plate positioned between a first component and a second component of the multifunctional semiconductor between which a compartmental shield is required. The mold chase is lowered into a molding position over the multifunctional semiconductor and a molding material is injected through an inlet sprue into the first and second cavities to surround the first and second components, respectively. After the molding material is cured, the mold chase is removed and an open trench is formed in the cured molding material by the trench plate. The open trench is filled with a conductive material to form the compartmental shield. A conformal shield may be added to cover the package.

Abstract: An integrated circuit has a substrate, a circuit, a core structure, a first encapsulation layer, a second encapsulation layer, and an oxide layer. The circuit includes transistors with active regions developed on the substrate and a metal layer formed above the active regions to provide interconnections for the transistors. The core structure is formed above the metal layer. The first encapsulation layer covers the core structure, and it has a first thermal expansion coefficient. The second encapsulation layer covers the first encapsulation layer over the core structure, and it has a second thermal expansion coefficient that is different from the first thermal expansion coefficient. As a part of the stress relief structure, the oxide layer is formed above the second encapsulation layer. The oxide layer includes an oxide thickness sufficient to mitigate a thermal stress between the first and second encapsulation layers.

Abstract: In some embodiments, the present disclosure relates to a method to form an integrated chip. The method may be performed by forming magnetic tunnel junction (MTJ) layers over a bottom electrode layer, and forming a sacrificial dielectric layer over the MTJ layers. The sacrificial dielectric layer is patterned to define a cavity, and a top electrode material is formed within the cavity. The sacrificial dielectric layer is removed and the MTJ layers are patterned according to the top electrode material to define an MTJ stack, after removing the sacrificial dielectric layer.

Abstract: A semiconductor structure can include a substrate comprising a first in-plane lattice constant, a graded layer on the substrate, and a first region of the graded layer comprising a first epitaxial oxide material comprising a second in-plane lattice constant. The graded layer on the substrate can include (Alx1Ga1?x1)y1Oz1, wherein x1 is from 0 to 1, wherein y1 is from 1 to 3, wherein z1 is from 2 to 4, and wherein x1 varies in a growth direction such that the graded layer has the first in-plane lattice constant adjacent to the substrate and a second in-plane lattice constant at a surface of the graded layer opposite the substrate. In some cases, a semiconductor structure includes a first region comprising a first epitaxial oxide material; a second region comprising a second epitaxial oxide material; and the graded region located between the first and the second regions.

Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.

Abstract: The invention relates to an optoelectronic component, which, in at least one embodiment, comprises an optoelectronic semiconductor chip having an emission side and a conversion element on the emission side. The conversion element is configured for conversion of a primary beam emitted by the semiconductor chip in operation as intended. The conversion element is divided into at least one first layer and one second layer. The first layer is arranged between the second layer and the emission side. The first layer comprises a first matrix material having fluorescent particles introduced therein. The second layer comprises a second matrix material having fluorescent particles introduced therein. The first matrix material of the first layer has a higher index of refraction than the second matrix material of the second layer.

Abstract: The present disclosure describes epitaxial oxide field effect transistors (FETs). In some embodiments, a FET comprises: a substrate comprising an oxide material; an epitaxial semiconductor layer on the substrate; a gate layer on the epitaxial semiconductor layer; and electrical contacts. In some cases, the epitaxial semiconductor layer can comprise a superlattice comprising a first and a second set of layers comprising oxide materials with a first and second bandgap. The gate layer can comprise an oxide material with a third bandgap, wherein the third bandgap is wider than the first bandgap. In some cases, the epitaxial semiconductor layer can comprise a second oxide material with a first bandgap, wherein the second oxide material comprises single crystal AxB1-xOn, wherein 0<x<1.0, wherein A is Al and/or Ga, wherein B is Mg, Ni, a rare earth, Er, Gd, Ir, Bi, or Li.

Abstract: There is described an optoelectronic device where each light-emitting diode has a wire-like shape. Spacing walls are formed so that the lateral sidewalls of each light-emitting diode are surrounded by at least one of the spacing walls. Light confinement walls directly cover the lateral sidewalls of the spacing walls by being in contact with the latter. The spacing walls have a convex-shaped outer face. At least one of the spacing walls has, over a lower portion, a thickness that increases when getting away from the substrate. They have, over an upper portion, a thickness that decreases at the level of the upper border of the light-emitting diode when getting away from the substrate. The light confinement walls have an inner face having a concave shape matching with the convex shape and directed towards the light-emitting diode for which it confines the light radiation thereof.

Abstract: A semiconductor light-emitting device includes first and second semiconductor layers and a light-emitting layer provided between the first semiconductor layer and the second semiconductor layer. The first semiconductor layer includes a compound semiconductor represented by a compositional formula AlXGa1-XAs (0<X<1). The first semiconductor layer has an n-type conductivity and includes a first impurity of the n-type. The first layer further includes carbon with a lower concentration than a concentration of the first impurity, and oxygen with a lower concentration than the concentration of the first impurity. The second semiconductor layer includes a compound semiconductor represented by a compositional formula AlYGa1-YAs (0<Y<1). The second semiconductor layer has a p-type conductivity and including a second impurity of the p-type. The second semiconductor layer further includes carbon with a concentration substantially equal to the carbon concentration in the first semiconductor layer.

Abstract: A phosphor-converted light-emitting device comprising an emitter device configured to emit a spectrum of electromagnetic radiation, a conversion layer comprising at least one phosphor, the conversion layer being configured to convert electromagnetic radiation of the spectrum into electromagnetic radiation of a different further spectrum, and a blocking layer configured to attenuate electromagnetic radiation outside the further spectrum, the conversion layer being arranged between the emitter device and the blocking layer.

Abstract: A nitride semiconductor light-emitting element includes an n-type cladding layer including n-type AlGaN, and an active layer that includes AlGaN and is located on the n-type cladding layer. Si concentration distribution in a direction of stacking the n-type cladding layer and the active layer has a local peak in the active layer.

Abstract: Described is a packaged component having a first surface and an opposite second surface. The packaged component may comprise a first element a second element, and a third element. The first element may have a first surface and an opposite second surface. The second element may have a first surface and an opposite second surface. The third element may electrically connect a portion of the first element to a portion of the second element. The second surface of the first element may be adjacent to the second surface of the packaged component, and the second surface of the second element may be adjacent to the second surface of the packaged component.

Abstract: A vertical light emitting diode structure with high current dispersion and high reliability comprises a conductive substrate with a central region and a side region; a light emitting semiconductor layer is disposed on the central region; an ohmic contact metal layer is disposed at a center of the light emitting semiconductor layer; an N-type electrode is disposed at the side region and is connected with the ohmic contact metal layer and the N-type electrode through an N-type electrode bridging structure; a working current is diffused from the center of the light emitting semiconductor layer to have high current dispersion, so that the problem of heat dissipation of local high current caused by the design that the N-type electrode is disposed on the edge can be solved.

Abstract: A memory device includes a semiconductor channel, a gate electrode, and a stack located between the semiconductor channel and the gate electrode. The stack includes, from one side to another, a first ferroelectric material portion, a second ferroelectric material portion, and a gate dielectric portion that contacts the semiconductor channel.

Abstract: A semiconductor device includes a substrate having PMOSFET and NMOSFET regions spaced apart from each other in a direction, a device isolation layer provided on the substrate that defines first and second active patterns respectively on the PMOSFET and NMOSFET regions, a gate electrode crossing the first and second active patterns, first and second source/drain patterns respectively provided on the first and second active patterns respectively and near the gate electrode, and an active contact extending in the direction and coupled to the first and second source/drain patterns. The active contact includes first and second body portions, which are respectively provided on the first and the second source/drain patterns, and a first protruding portion and a recessed portion, which are provided between the first and second body portions and on the device isolation layer between the PMOSFET and NMOSFET regions. The recessed portion has an upwardly recessed bottom.

Abstract: A semiconductor device in which a semiconductor element mounted on a laminate substrate and an electrically conductive connection member are sealed with a sealing material, includes: a primer layer in an interface between the sealing material and sealed members including the laminate substrate, the semiconductor element, and the electrically conductive connection member, in which the sealing material includes a first sealing layer which is provided in contact with the primer layer; and a second sealing layer which covers the first sealing layer, the semiconductor device satisfies ?p??1>?2 in which ?p, ?1, and ?2 represent coefficients of linear thermal expansion of the primer layer, the first sealing layer, and the second sealing layer, respectively, ?c?15×10?6/° C. in which ?c represents a composite coefficient of linear thermal expansion of the sealing layers, and Ec?5 GPa or more in which Ec represents a composite Young's modulus of the sealing layers.

Abstract: Provided is a semiconductor light emitting device including a growth substrate; a pillar-shaped semiconductor layer formed on the growth substrate; and a buried semiconductor layer formed to cover the pillar-shaped semiconductor layer, wherein the pillar-shaped semiconductor layer has an n-type nanowire layer formed at a center, an active layer formed on an outermore side than the n-type nanowire layer, a p-type semiconductor layer formed on an outermore side than the active layer and a tunnel junction layer formed on an outermore side than the p-type semiconductor layer, and wherein at least a part of the pillar-shaped semiconductor layer is provided with a removed region formed by removing from the buried semiconductor layer to a part of the tunnel junction layer.