Abstract: Embodiments of the present disclosure relate to a light-emitting device package and an electronic device. In an embodiment, a light-emitting device package is provided that includes a lead frame, at least two light-emitting devices mounted on the lead frame and configured to emit different wavelengths of a same color of light, and a phosphor configured to emit light having a color different from the color of light emitted from the at least two light-emitting devices. The embodiments of the present disclosure also relate to an electronic device including the light-emitting device package as a light source. According to the embodiments of the present disclosure, various expressible color spaces can be selectively expressed.

Abstract: A MEMS component includes a semiconductor substrate stack having a first semiconductor substrate and a second semiconductor substrate, wherein the semiconductor substrate stack has a cavity formed within the first and second semiconductor substrates, and wherein at least the first or the second semiconductor substrate has an access opening for gas exchange between the cavity and an environment. A radiation source is arranged at the first semiconductor substrate, and a radiation detector is arranged at the second semiconductor substrate. Two mutually spaced apart reflection elements are arranged in a beam path between the radiation source and the radiation detector, wherein one reflection element is partly transmissive to the emitted radiation from the cavity in the direction of the radiation detector, and wherein an interspace between the two mutually spaced apart reflection elements has a length that is at least ten times the wavelength of the emitted radiation.

Abstract: A semiconductor light-emitting device includes a light-emitting structure including a first semiconductor layer, an active layer, and a second semiconductor layer which are sequentially stacked, a first insulating layer on the second semiconductor layer with a plurality of first openings having first widths and a plurality of second openings having second widths different from the first widths, a first electrode electrically connected to the first semiconductor layer through the first openings, a first sub-electrode layer between the second semiconductor layer and the first insulating layer, the first sub-electrode layer being exposed through the second openings, and a second sub-electrode layer on the first insulating layer, the second sub-electrode layer being connected to the first sub-electrode layer through the second openings, wherein a first distance between the first openings closest to each other is different from a second distance between the second openings closest to each other.

Abstract: A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.

Abstract: A light-emitting device having four or more LEDs arranged on a substrate includes a first color conversion layer and a second color conversion layer. The first color conversion layer is continuously formed on light exit surfaces of two or more of the LEDs, and the second color conversion layer is continuously formed on light exit surfaces of two or more of the LEDs that are different from the LEDs on which the first color conversion layer is formed.

Abstract: A light-emitting device includes a composite structure having a phosphor crystal sheet and phosphor crystal powders on the phosphor crystal sheet. A light-emitting unit of the device is disposed under a side of the phosphor crystal sheet that is opposite to a side of the phosphor crystal powders. A problem of blue-enriched white light may be tackled.

Abstract: A phosphor is represented by a chemical formula of Lu(3-x-z)MgxZnyAl(5-y)O12:Cez, in which in a case where z is in a range of 0.01?z?0.03, x and y respectively satisfy 0<x?1.4 and 0<y?1.4, in a case where z is in a range of 0.03<z?0.06, x and y respectively satisfy y<0.2 and 0.1?x?1.4, x<0.2 and 0.1?y?1.4, or x=0.2 and y=0.2, in a case where z is in a range of 0.06<z?0.09, x and y respectively satisfy y<0.2 and 0.1?x<1.4, or x<0.2 and 0.1?y<1.4, and in a case where z is in a range of 0.09<z?0.12, x and y respectively satisfy y<0.2 and 0.1?x<0.9, or x<0.2 and 0.1?y<0.9.

Abstract: The invention relates to various aspects of a ?-LED or a ?-LED array for augmented reality or lighting applications, in particular in the automotive field. The ?-LED is characterized by particularly small dimensions in the range of a few ?m.

Abstract: A semiconductor structure includes a substrate, a bottom source/drain region disposed on a top surface of the substrate, and a plurality of fins disposed over a top surface of the bottom source/drain region. The fins provide vertical transport channels for one or more vertical transport field-effect transistors. The semiconductor structure also includes at least one self-aligned shared contact disposed between an adjacent pair of the plurality of fins. The adjacent pair of the plurality of fins includes a first fin providing a first vertical transport channel for a first vertical transport field-effect transistor and a second fin providing a second vertical transport channel for a second vertical transport field-effect transistor.

Abstract: Embodiments of source structure of a three-dimensional (3D) memory device and method for forming the source structure of the 3D memory device are disclosed. In an example, a NAND memory device includes a substrate, an alternating conductor/dielectric stack, a NAND string, a source conductor layer, and a source contact. The alternating conductor/dielectric stack includes a plurality of conductor/dielectric pairs above the substrate. The NAND string extends vertically through the alternating conductor/dielectric stack. The source conductor layer is above the alternating conductor/dielectric stack and is in contact with an end of the NAND string. The source contact includes an end in contact with the source conductor layer. The NAND string is electrically connected to the source contact by the source conductor layer. In some embodiments, the source conductor layer includes one or more conduction regions each including one or more of a metal, a metal alloy, and a metal silicide.

Abstract: A method of forming a semiconductor structure includes forming a plurality of fins over a top surface of a bottom source/drain region disposed over a top surface of a substrate, the fins providing vertical transport channels for a plurality of vertical transport field-effect transistors. The method also includes forming a first gate conductor surrounding a first one of an adjacent pair of the plurality of fins providing a first vertical transport channel for a first vertical transport field-effect transistor, forming a second gate conductor surrounding a second one of the adjacent pair of the plurality of fins providing a second vertical transport channel for a second vertical transport field-effect transistor, and forming at least one shared gate contact to the first gate conductor and the second gate conductor, the at least one shared gate contact being formed at first ends of the adjacent pair of the plurality of fins.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to contact structures and methods of manufacture. The method includes: recessing an isolation region between adjacent gate structures and below metallization overburden of source/drain metallization; planarizing the metallization overburden to a level of the adjacent gate structures; and forming source/drain contacts to the source/drain metallization, on sides of and extending above the adjacent gate structures.

Abstract: A semiconductor device includes a semiconductor stack having a first-type semiconductor structure, an active structure, and a second-type semiconductor structure disposed on the first-type semiconductor structure. The second-type semiconductor structure has a doping concentration. A first portion includes a part of the first-type semiconductor structure, the active structure, and the second-type semiconductor structure, and has a current confining region. A second portion includes a part of the first-type semiconductor structure, the active structure, and the second-type semiconductor structure, and includes a first-type heavily doped region in the second-type semiconductor structure. The first-type heavily doped region includes a doping concentration higher than that of the second-type semiconductor structure.

Abstract: A semiconductor memory device includes a substrate, gate electrodes arranged in a thickness direction of the substrate, first and second semiconductor layers, a gate insulating film, and a first contact. The first semiconductor layer extends in the thickness direction and faces the gate electrodes. The gate insulating film is between the gate electrodes and the first semiconductor layer. The second semiconductor layer is between the substrate and the gate electrodes and connected to a side surface of the first semiconductor layer in a surface direction. The first contact extends in the thickness direction and electrically connected to the second semiconductor layer. The second semiconductor layer includes a first region in contact with the side surface of the first semiconductor layer and containing P-type impurities, and a first contact region electrically connected to the first contact and having a higher concentration of N-type impurities than the first region.

Abstract: A semiconductor device includes a first type semiconductor structure, an active structure, and a contact layer. The first type semiconductor structure includes a first lattice constant, a first side and a second side opposite to the first side. The active structure is on the first side of the first type semiconductor structure and emits a radiation, and the radiation has a peak wavelength between 1000 nm and 2000 nm. The contact layer is on the second side of the first type semiconductor structure and includes a second lattice constant. A difference between the first lattice constant and the second lattice constant is at least 0.5%.

Abstract: Some embodiments include an integrated assembly having a semiconductor die with memory array regions and one or more regions peripheral to the memory array regions. A stack of alternating insulative and conductive levels extends across the memory array regions and passes into at least one of the peripheral regions. The stack generates bending stresses on the die. At least one stress-moderating region extends through the stack and is configured to alleviate the bending stresses.

Abstract: A light emitting device is provided. The light emitting device includes a first semiconductor layer; a second semiconductor layer provided on a bottom surface of the first semiconductor layer; an active layer interposed between the first semiconductor layer and the second semiconductor layer; a dielectric layer provided on a bottom surface of the second semiconductor layer; a plurality of first n-contacts provided on a first etched surface of the first semiconductor layer; and a plurality of first p-contacts and a plurality of second p-contacts provided on the bottom surface of the second semiconductor layer. One first n-contact is disposed along a first edge region of the first semiconductor layer, one first p-contact is closer to the one first n-contact than one second p-contact, and an area of the one first p-contact is greater than an area of each of the second p-contacts.

Abstract: An image sensing device in which overlay pixels are formed in a dummy pixel region is disclosed. The image sensing device includes a first dummy pixel region including a first micro-lens, a second dummy pixel region surrounding the first dummy pixel region and formed without micro-lens, and a third dummy pixel region surrounding the second dummy pixel region and including a plurality of second micro-lenses. A center point of the first micro-lens is aligned with a center point of the first photoelectric conversion element, and a center point of the second micro-lenses is shifted in a certain direction from a center point of the third photoelectric conversion elements.

Abstract: An integrated circuit (IC) device includes an electrode, a dielectric layer facing the electrode, and a plurality of interface layers interposed between the electrode and the dielectric layer and including a first metal. The plurality of interface layers includes a first interface layer and a second interface layer. An oxygen content of the first interface layer is different from an oxygen content of the second interface layer.

Abstract: A semiconductor optical device includes an element structure layer that includes a mesa stripe extending in a first direction; an electrode film that covers at least an upper surface of the mesa stripe; an electrode pad portion that covers a part of a first region positioned in a second direction, intersecting the first direction, relative to the mesa stripe on an upper surface of the element structure layer and is electrically connected to the electrode film; a first dummy electrode that covers another part of the first region and is electrically insulated from the electrode film; and a second dummy electrode that covers at least a part of a second region positioned in a third direction, opposite to the second direction, relative to the mesa stripe on the upper surface of the element structure layer and is electrically insulated from the electrode film, wherein the first dummy electrode includes a first portion disposed in the first direction relative to the electrode pad portion and a second portion dispose