Patents Examined by Masud K Khan
  • Patent number: 12001334
    Abstract: A uniform cache for fast data access including a plurality of compute units (CUs) and a plurality of L0 caches with an arrangement in a network configuration where each one of CUs is surrounded by a first group of the plurality of L0 caches and each of the plurality of L0 caches is surrounded by a L0 cache group and CU group. One of CUs, upon a request for data, queries the surrounding first group of L0 caches to satisfy the request. If the first group of L0 caches fails to satisfy the data request, the first group of the plurality of L0 caches queries a second group of adjacent LO caches to satisfy the request. If the second group of adjacent L0 caches fails to satisfy the data request, the second group of adjacent L0 caches propagating the query to the next group of L0 caches.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: June 4, 2024
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Dazheng Wang, Xuwei Chen
  • Patent number: 12001282
    Abstract: In described examples, a processor system includes a processor core that generates memory write requests, and a cache memory with a memory controller having a memory pipeline. The cache memory has cache lines of length L. The cache memory has a minimum write length that is less than a cache line length of the cache memory. The memory pipeline determines whether the data payload includes a first chunk and ECC syndrome that correspond to a partial write and are writable by a first cache write operation, and a second chunk and ECC syndrome that correspond to a full write operation that can be performed separately from the first cache write operation. The memory pipeline performs an RMW operation to store the first chunk and ECC syndrome in the cache memory, and performs the full write operation to store the second chunk and ECC syndrome in the cache memory.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: June 4, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Abhijeet Ashok Chachad, Timothy David Anderson, David Matthew Thompson, Daniel Brad Wu
  • Patent number: 11994999
    Abstract: A method, computer program product, and computing system for generating a page buffer pool within a data journal of a storage node. A plurality of IO operations may be processed on a storage array using the storage node. A plurality of pages may be persisted in a plurality of page buffers within the page buffer pool based upon, at least in part, the processing of the plurality of IO operations. For each page buffer in the page buffer pool, a hash of the page buffer may be generated, thus defining a page buffer hash. The page buffer hash may be stored in a page descriptor associated with the page buffer.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: May 28, 2024
    Assignee: Dell Products L.P.
    Inventors: Oran Baruch, Vladimir Shveidel, Alexander Shknevsky
  • Patent number: 11994993
    Abstract: An adaptive prefetcher for a shared system cache of a processing system including multiple requestors having a cache miss monitor and a prefetch controller. The cache miss monitor monitors requests for information from memory and identifies one of the requestors for which an identified cache line is requested. The prefetch controller submits an adaptive request for a subsequent cache line. The subsequent cache line may be determined based on a latency comparison between a loop latency (LL) of the prefetch controller and a stream latency (SL) of the identified requestor. A latency memory may be included that stores stream latencies for the requestors. The latency comparison may be used to determine how many cache lines to skip relative to the identified cache line, such as according to SL*SK<LL?SL*(SK+1) in which SK is the number of cache lines to skip.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: May 28, 2024
    Assignee: NXP B.V.
    Inventors: Xiao Sun, Xiaotao Chen, Rohit Kumar Kaul
  • Patent number: 11977755
    Abstract: A front-end firmware component of a memory sub-system receives a first request to perform a first set of initialization operations and initiates a first set of initialization operations for the front-end component in parallel with initiating a second set of initialization operations for a back-end component. Responsive to completing the first set of initialization operations, the front-end component sends a first notification to a host computer system to indicate that the front-end component is available to respond to requests for configuration data associated with the memory sub-system, receives a second request from the host computer system for a configuration data associated with the memory sub-system, and responsive to receiving the second request from the host computer system before the back-end component has completed the second set of initialization operations, provides the configuration data to the host computer system.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: May 7, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Ximin Shan, Venkata Naga Lakshman Pasala, Noorshaheen Mavungal Noorudheen
  • Patent number: 11960766
    Abstract: A data storage device and method for accidental delete protection are provided. In one embodiment, a data storage device comprises a memory and a controller. The memory comprises a first set of physical blocks and a second set of physical blocks, where the first and second sets of physical blocks are associated with separate logical-to-physical address tables and/or separate block lists. The controller is configured to write data received from a host in the first set of physical blocks and move the data from the first set of physical blocks to the second set of physical blocks in response to the host requesting that a modified version of the data be written in the memory. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: April 16, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Abhinandan Venugopal, Amit Sharma
  • Patent number: 11954337
    Abstract: A method, a computer program product, and a system for initializing components to monitor for unauthorized encryptions of filesystem objects stored on a computing system. The method includes configuring an encryption monitor register to establish monitoring preferences of filesystem objects and allocating a predetermined size of persistent memory as a backup memory area for storing pre-encrypted versions of the filesystem objects. The method also includes inserting a starting address of the backup memory area in data bits of the encryption monitor register, and setting encryption monitor bits of page table entries in a hardware page table that correspond to at least one filesystem object, thereby establishing encryption monitoring of the filesystem object.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: April 9, 2024
    Assignee: International Business Machines Corporation
    Inventors: Ramanjaneya Sarma Burugula, Joefon Jann, Niteesh Kumar Dubey, Ching-Farn Eric Wu
  • Patent number: 11954350
    Abstract: A storage device includes a memory device, and a memory controller configured to receive data and a log related to a property of the data from an external host, allocate a super block in which the data in the memory device is to be stored and a physical zone in the super block based on the log of the data, and store information for the log of the data stored for each physical zone and a time point at which a physical zone of a full state in which an empty area does not exist is switched to the full state. The memory controller controls the memory device to perform garbage collection according to the number of physical zones of an empty state, and selects a victim physical zone based on the information for the log of the data and a full state switch time point.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: April 9, 2024
    Assignee: SK hynix Inc.
    Inventors: Soon Yeal Yang, Jung Ki Noh
  • Patent number: 11947460
    Abstract: Apparatus, method and code for fabrication of the apparatus, the apparatus comprising a cache providing a plurality of cache lines, each cache line storing a block of data; cache access control circuitry, responsive to an access request, to determine whether a hit condition is present in the cache; and cache configuration control circuitry to set, in response to a merging trigger event, merge indication state identifying multiple cache lines to be treated as a merged cache line to store multiple blocks of data, wherein when the merge indication state indicates that the given cache line is part of the merged cache line, the cache access control circuitry is responsive to detecting the hit condition to allow access to any of the data blocks stored in the multiple cache lines forming the merged cache line.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: April 2, 2024
    Assignee: Arm Limited
    Inventors: Vladimir Vasekin, David Michael Bull, Vincent Rezard, Anton Antonov
  • Patent number: 11947428
    Abstract: Techniques are disclosed relating to archive operations for database systems. In some embodiments, a database system initiates one or more archive operations to archive one or more data extents for a database maintained by the database system. The system may halt archive activity for the database, in response to determining that archive operations for a threshold amount of data extents are initiated but not completed. The system may cancel at least one of the one or more archive operations. The system may determine to resume activity for the database based on determining that a threshold timer interval has elapsed and determining that a threshold amount of storage space is available for the database system. Disclosed embodiments may improve database availability, relative to traditional techniques.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: April 2, 2024
    Assignee: Salesforce, Inc.
    Inventors: Steven Raspudic, Hefeng Yuan, Jeffrey Alexander Zoch, Goutham Meruva, Praveenkumar Bagavathiraj
  • Patent number: 11940925
    Abstract: A logical-to-physical (L2P) data structure comprising a plurality of L2P table entries is maintained on the volatile memory device. Each L2P table entry comprises a block number and a page table index corresponding to the non-volatile memory device. A plurality of physical-to-logical (P2L) data structures each comprising a plurality of P2L table entries is maintained on the volatile memory device. Each of the plurality of P2L data structures corresponds to a portion of the L2P data structure.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: March 26, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Meng Wei
  • Patent number: 11928031
    Abstract: An illustrative data storage management system enables a Tenant to retain control over criteria for protecting the Tenant's data, and hides details of the Service Provider's infrastructure. The Service Provider may have many data centers, each one represented within the system by a Resource Pool with attributes that reflect the infrastructure resources of the corresponding data center. A system analysis, which is triggered by the Tenant's choices for data protection, keys in on a suitable Resource Pool. The system analysis identifies suitable system resources within the Resource Pool and associates them to the data source. Subsequent data protection jobs invoke proper system components based on the associations created by the system analysis. In some embodiments, the system will invoke infrastructure resources created on demand when a data protection job is initiated rather than being pre-existing resources.
    Type: Grant
    Filed: January 25, 2023
    Date of Patent: March 12, 2024
    Assignee: Commvault Systems, Inc.
    Inventors: Bhavyan Bharatkumar Mehta, Anand Vibhor, Niteen Jain
  • Patent number: 11928357
    Abstract: Embodiments of this application provide a method and system for adjusting a memory, and a semiconductor device. The method for adjusting a memory includes: acquiring a mapping relationship among a temperature of a transistor, a substrate bias voltage of a sense amplification transistor in a sense amplifier, and an actual data writing time of the memory; acquiring a current temperature of the transistor; and adjusting the substrate bias voltage on the basis of the current temperature and the mapping relationship, such that an actual data writing time corresponding to an adjusted substrate bias voltage is within a preset writing time.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: March 12, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Shu-Liang Ning, Jun He, Zhan Ying, Jie Liu
  • Patent number: 11921640
    Abstract: A cache may store critical cache lines and non-critical cache lines, and may attempt to retain critical cache lines in the cache by, for example, favoring the critical cache lines in replacement data updates, retaining the critical cache lines with a certain probability when victim cache blocks are being selected, etc. Criticality values may be retained at various levels of the cache hierarchy. Additionally, accelerated eviction may be employed if the threads previously accessing the critical cache blocks are viewed as dead.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: March 5, 2024
    Assignee: Apple Inc.
    Inventors: Tyler J. Huberty, Vivek Venkatraman, Sandeep Gupta, Eric J. Furbish, Srinivasa Rangan Sridharan, Stephan G. Meier
  • Patent number: 11899584
    Abstract: Embodiments of the present disclosure relate to a system and an operating method of the system. Based on some embodiments of the disclosed technology, the system may include a random access memory structured to include memory cells to store data, a cache memory configured to cache at least part of the data, and a processor in communication with the random access memory and the cache memory to access at least part of the data from the random access memory or cache memory. The system may determine a cache hit ratio for the cache memory, and may set an operating frequency of the random access memory based on the cache hit ratio.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: February 13, 2024
    Assignee: SK HYNIX INC.
    Inventors: Yong Wan Hwang, Nam Hyeok Jeong, Kwang Ho Choi, Moon Hyeok Choi, Tae Woong Ha
  • Patent number: 11899591
    Abstract: Exemplary methods, apparatuses, and systems include detecting an operation to write dirty data to a cache. The cache is divided into a plurality of channels. In response to the operation, the dirty data is written to a first cache line in the cache, the first cache line being accessed via a first channel. Additionally, a redundant copy of the dirty data is written to a second cache line in the cache. The second cache line serves as a redundant write buffer and is accessed via a second channel, the first and second channels differing from one another. A metadata entry for the second cache line is updated to reference a location of the dirty data in the first cache line.
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: February 13, 2024
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Cagdas Dirik, Robert M. Walker
  • Patent number: 11892982
    Abstract: Systems and methods for reducing delays between the time at which a need for a resynchronization of data replication between a volume of a local CG and its peer volume of a remote CG is detected and the time at which the resynchronization is triggered (Reseed Time Period) are provided. According to an example, information indicative of the direction of data replication between the volume and the peer volume is maintained within a cache of a node. Responsive to a disruptive operation (e.g., relocation of the volume from an original node to a new node), the Reseed Time Period is lessened by proactively adding a passive cache entry to a cache within the new node at the time the CG relationship is created when the new node represents an HA partner of the original node and prior to the volume coming online when the new node represents a non-HA partner.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: February 6, 2024
    Assignee: NetApp, Inc.
    Inventors: Murali Subramanian, Sohan Shetty, Rakesh Bhargava, Akhil Kaushik
  • Patent number: 11886342
    Abstract: A method, system, and computer program product for augmenting cache replacement operations are provided. The method identifies a set of cache lines within a first cache level of a multilevel cache. A first candidate cache line is identified based on a first replacement scheme of the first cache level. A second candidate cache line is identified based on the first replacement scheme of the first cache level. A replacement cache line is selected for replacement in the first cache level. The replacement cache line is selected from the first candidate cache line and the second candidate cache line and based on the first replacement scheme of the first cache level and a second replacement scheme of a second cache level. The method removes the replacement cache line from the first cache level.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: January 30, 2024
    Assignee: International Business Machines Corporation
    Inventors: Aaron Dingler, Mohit Karve, Alper Buyuktosunoglu
  • Patent number: 11875046
    Abstract: A method includes sending an enumeration of a resource unit of the computing device to a first computing system tenant and to a second computing system tenant. The enumeration is sent through a first protocol and indicating a managing protocol associated with managing the resource unit. The method further includes receiving a first request from the first computing system tenant to reserve the resource unit. The first request is received through the managing protocol. The method further includes receiving a second request from the second computing system tenant to reserve the resource unit. The second request is received through the managing protocol. The method further includes sending, to the second computing system tenant, an indication that the resource unit is reserved by the first computing system tenant. The indication is sent through the managing protocol.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: January 16, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Daniel Lee Helmick
  • Patent number: 11861199
    Abstract: Techniques are provided for data management across a persistent memory tier and a file system tier. A block within a persistent memory tier of a node is determined to have up-to-date data compared to a corresponding block within a file system tier of the node. The corresponding block may be marked as a dirty block within the file system tier. Location information of a location of the block within the persistent memory tier is encoded into a container associated with the corresponding block. In response to receiving a read operation, the location information is obtained from the container. The up-to-date data is retrieved from the block within the persistent memory tier using the location information for processing the read operation.
    Type: Grant
    Filed: July 24, 2022
    Date of Patent: January 2, 2024
    Assignee: NetApp, Inc.
    Inventors: Ananthan Subramanian, Matthew Fontaine Curtis-Maury, Ram Kesavan, Vinay Devadas