Abstract: A method of using boot-time metadata in a storage system is provided. The method includes writing a fragmentation stride to a solid-state storage device of the storage system, the fragmentation stride defining a granularity on which fragmentation of erase blocks of the solid-state storage device occurs. The method includes allocating portions of erase blocks for at least one process in the storage system, in accordance with the fragmentation stride and writing boot up metadata at offsets that are based on the fragmentation stride, in the solid-state storage device.

Abstract: A storage system forms an allocation unit for writing into solid-state storage memory. The allocation unit is formed from at least a portion of a first erase block and a first sub block of a partitioned second erase block. The system forms multiple subsequent allocation units. Each subsequent allocation unit is formed from a remaining second sub block of a partitioned erase block and at least a portion of a next erase block. Forming the subsequent allocation units consumes each of multiple erase blocks in a cascading sequence. The system allocates the allocation unit and the subsequent allocation units for writing in the storage system.

Abstract: Disclosed herein are an apparatus and a method for selecting a storage location based on data usage. The apparatus for selecting a storage location based on data usage includes memory for storing at least one program, and a processor for executing the program, wherein the program is configured to, when an instruction for predetermined data is input through a user interface, determine one of multiple storage devices based on a result of analysis of usage of the predetermined data, and perform a process corresponding to the instruction by writing the predetermined data to the determined storage device or by reading the predetermined data from the determined storage device, and, wherein the multiple storage devices comprise at least two of multiple different types of permanent storage devices and multiple different types of volatile storage devices.

Abstract: Systems and methods are described herein for an efficient storage layout of recorded content associated with a particular user. Content segments, unique to the user and encoded/transcoded at different bit rates, may be stored/partitioned based on the likelihood of a particular bit rate version of content being requested by the user and a duration of playback for the content segment. Content that is more frequently requested may be concatenated in a single storage location on more high performance hardware. Further, content that is played back for a longer duration of playback may also be grouped together and stored on more high performance hardware. Content that is more likely to be played for only a short time may be stored within a plurality of storage containers.

Abstract: In a method of scheduling commands for a memory device including a plurality of storage regions, a plurality of host commands used to access the plurality of storage regions are received from a host device. The plurality of host commands are queued in a first command queue. A first scheduling associated with the plurality of host commands is performed based on a mapping table and operation states of the plurality of storage regions. The mapping table includes a correspondence between the plurality of host commands and the plurality of storage regions. The plurality of host commands are executed based on a result of the first scheduling. In response to a bank collision occurring while the plurality of host commands are executed, a second scheduling associated with the plurality of host commands is performed.

Abstract: System and techniques for evicting a cache line with pending control request are described herein. A memory request—that includes an address corresponding to a set of cache lines—can be received. A determination can be made that a cache line of the set of cache lines will be evicted to process the memory request. Another determination can be made that a control request has been made to a host from the memory device and that the control request pending when it is determined that the cache line will be evicted. Here, a counter corresponding to the set of cache lines can be incremented (e.g., by one) to track the pending control request in face of eviction. Then, the cache line can be evicted.

Abstract: A uniform cache for fast data access including a plurality of compute units (CUs) and a plurality of L0 caches with an arrangement in a network configuration where each one of CUs is surrounded by a first group of the plurality of L0 caches and each of the plurality of L0 caches is surrounded by a L0 cache group and CU group. One of CUs, upon a request for data, queries the surrounding first group of L0 caches to satisfy the request. If the first group of L0 caches fails to satisfy the data request, the first group of the plurality of L0 caches queries a second group of adjacent LO caches to satisfy the request. If the second group of adjacent L0 caches fails to satisfy the data request, the second group of adjacent L0 caches propagating the query to the next group of L0 caches.

Abstract: In described examples, a processor system includes a processor core that generates memory write requests, and a cache memory with a memory controller having a memory pipeline. The cache memory has cache lines of length L. The cache memory has a minimum write length that is less than a cache line length of the cache memory. The memory pipeline determines whether the data payload includes a first chunk and ECC syndrome that correspond to a partial write and are writable by a first cache write operation, and a second chunk and ECC syndrome that correspond to a full write operation that can be performed separately from the first cache write operation. The memory pipeline performs an RMW operation to store the first chunk and ECC syndrome in the cache memory, and performs the full write operation to store the second chunk and ECC syndrome in the cache memory.

Abstract: A method, computer program product, and computing system for generating a page buffer pool within a data journal of a storage node. A plurality of IO operations may be processed on a storage array using the storage node. A plurality of pages may be persisted in a plurality of page buffers within the page buffer pool based upon, at least in part, the processing of the plurality of IO operations. For each page buffer in the page buffer pool, a hash of the page buffer may be generated, thus defining a page buffer hash. The page buffer hash may be stored in a page descriptor associated with the page buffer.

Abstract: An adaptive prefetcher for a shared system cache of a processing system including multiple requestors having a cache miss monitor and a prefetch controller. The cache miss monitor monitors requests for information from memory and identifies one of the requestors for which an identified cache line is requested. The prefetch controller submits an adaptive request for a subsequent cache line. The subsequent cache line may be determined based on a latency comparison between a loop latency (LL) of the prefetch controller and a stream latency (SL) of the identified requestor. A latency memory may be included that stores stream latencies for the requestors. The latency comparison may be used to determine how many cache lines to skip relative to the identified cache line, such as according to SL*SK<LL?SL*(SK+1) in which SK is the number of cache lines to skip.

Abstract: A front-end firmware component of a memory sub-system receives a first request to perform a first set of initialization operations and initiates a first set of initialization operations for the front-end component in parallel with initiating a second set of initialization operations for a back-end component. Responsive to completing the first set of initialization operations, the front-end component sends a first notification to a host computer system to indicate that the front-end component is available to respond to requests for configuration data associated with the memory sub-system, receives a second request from the host computer system for a configuration data associated with the memory sub-system, and responsive to receiving the second request from the host computer system before the back-end component has completed the second set of initialization operations, provides the configuration data to the host computer system.

Abstract: A data storage device and method for accidental delete protection are provided. In one embodiment, a data storage device comprises a memory and a controller. The memory comprises a first set of physical blocks and a second set of physical blocks, where the first and second sets of physical blocks are associated with separate logical-to-physical address tables and/or separate block lists. The controller is configured to write data received from a host in the first set of physical blocks and move the data from the first set of physical blocks to the second set of physical blocks in response to the host requesting that a modified version of the data be written in the memory. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A storage device includes a memory device, and a memory controller configured to receive data and a log related to a property of the data from an external host, allocate a super block in which the data in the memory device is to be stored and a physical zone in the super block based on the log of the data, and store information for the log of the data stored for each physical zone and a time point at which a physical zone of a full state in which an empty area does not exist is switched to the full state. The memory controller controls the memory device to perform garbage collection according to the number of physical zones of an empty state, and selects a victim physical zone based on the information for the log of the data and a full state switch time point.

Abstract: A method, a computer program product, and a system for initializing components to monitor for unauthorized encryptions of filesystem objects stored on a computing system. The method includes configuring an encryption monitor register to establish monitoring preferences of filesystem objects and allocating a predetermined size of persistent memory as a backup memory area for storing pre-encrypted versions of the filesystem objects. The method also includes inserting a starting address of the backup memory area in data bits of the encryption monitor register, and setting encryption monitor bits of page table entries in a hardware page table that correspond to at least one filesystem object, thereby establishing encryption monitoring of the filesystem object.

Abstract: Techniques are disclosed relating to archive operations for database systems. In some embodiments, a database system initiates one or more archive operations to archive one or more data extents for a database maintained by the database system. The system may halt archive activity for the database, in response to determining that archive operations for a threshold amount of data extents are initiated but not completed. The system may cancel at least one of the one or more archive operations. The system may determine to resume activity for the database based on determining that a threshold timer interval has elapsed and determining that a threshold amount of storage space is available for the database system. Disclosed embodiments may improve database availability, relative to traditional techniques.

Abstract: Apparatus, method and code for fabrication of the apparatus, the apparatus comprising a cache providing a plurality of cache lines, each cache line storing a block of data; cache access control circuitry, responsive to an access request, to determine whether a hit condition is present in the cache; and cache configuration control circuitry to set, in response to a merging trigger event, merge indication state identifying multiple cache lines to be treated as a merged cache line to store multiple blocks of data, wherein when the merge indication state indicates that the given cache line is part of the merged cache line, the cache access control circuitry is responsive to detecting the hit condition to allow access to any of the data blocks stored in the multiple cache lines forming the merged cache line.

Abstract: A logical-to-physical (L2P) data structure comprising a plurality of L2P table entries is maintained on the volatile memory device. Each L2P table entry comprises a block number and a page table index corresponding to the non-volatile memory device. A plurality of physical-to-logical (P2L) data structures each comprising a plurality of P2L table entries is maintained on the volatile memory device. Each of the plurality of P2L data structures corresponds to a portion of the L2P data structure.

Abstract: An illustrative data storage management system enables a Tenant to retain control over criteria for protecting the Tenant's data, and hides details of the Service Provider's infrastructure. The Service Provider may have many data centers, each one represented within the system by a Resource Pool with attributes that reflect the infrastructure resources of the corresponding data center. A system analysis, which is triggered by the Tenant's choices for data protection, keys in on a suitable Resource Pool. The system analysis identifies suitable system resources within the Resource Pool and associates them to the data source. Subsequent data protection jobs invoke proper system components based on the associations created by the system analysis. In some embodiments, the system will invoke infrastructure resources created on demand when a data protection job is initiated rather than being pre-existing resources.

Abstract: Embodiments of this application provide a method and system for adjusting a memory, and a semiconductor device. The method for adjusting a memory includes: acquiring a mapping relationship among a temperature of a transistor, a substrate bias voltage of a sense amplification transistor in a sense amplifier, and an actual data writing time of the memory; acquiring a current temperature of the transistor; and adjusting the substrate bias voltage on the basis of the current temperature and the mapping relationship, such that an actual data writing time corresponding to an adjusted substrate bias voltage is within a preset writing time.

Abstract: A cache may store critical cache lines and non-critical cache lines, and may attempt to retain critical cache lines in the cache by, for example, favoring the critical cache lines in replacement data updates, retaining the critical cache lines with a certain probability when victim cache blocks are being selected, etc. Criticality values may be retained at various levels of the cache hierarchy. Additionally, accelerated eviction may be employed if the threads previously accessing the critical cache blocks are viewed as dead.