Abstract: The present disclosure relates to field of Dual In-Line Memory Modules that discloses method and system for generating memory maps. The method comprises detecting, by computing system, at least one of DIMM and one or more Dynamic Random Access Memory (DRAM) chips associated with computing system. The one or more accelerators are configured in at least one of DIMM and one or more DRAM chips. Further, the method includes determining accelerator information for each of one or more accelerators via at least one of Serial Presence Detect (SPD) and Multi-Purpose Register (MPR) associated with at least one of DIMM and one or more DRAM chips. Method includes generating unique memory map for each of one or more accelerators based on accelerator information of corresponding one or more accelerators. As a result, performance of computing system may be improved as accelerator capabilities of one or more accelerators are effectively utilized.

Abstract: A method includes sending an enumeration of a resource unit of the computing device to a first computing system tenant and to a second computing system tenant. The enumeration is sent through a first protocol and indicating a managing protocol associated with managing the resource unit. The method further includes receiving a first request from the first computing system tenant to reserve the resource unit. The first request is received through the managing protocol. The method further includes receiving a second request from the second computing system tenant to reserve the resource unit. The second request is received through the managing protocol. The method further includes sending, to the second computing system tenant, an indication that the resource unit is reserved by the first computing system tenant. The indication is sent through the managing protocol.

Abstract: A method of using flash storage devices with different sized erase blocks is provided. The method includes allocating a plurality of erase blocks of heterogeneous erase block sizes to a RAID stripe, to form a tile pattern having the heterogeneous erase block sizes in the RAID stripe. The method includes writing the RAID stripe across the flash storage devices in accordance with the allocating, and stopping the writing the RAID stripe, responsive to contents of the RAID stripe reaching a threshold.

Abstract: Provided is a computer system capable of maintaining a storage capacity allocated to a journal volume within an appropriate range during an application period of remote copy. A first storage system includes a primary volume and a primary journal volume, and a second storage system includes a secondary volume and a secondary journal volume. A management computer is configured to manage the remote copy in which a primary volume, a primary journal volume, a secondary journal volume, and a secondary volume are paired, and expand and/or release a capacity of the primary journal volume and/or the secondary journal volume according to operation information of a resource related to the remote copy.

Abstract: A technique for accurate communication between a non-volatile memory and its controller. The controller accesses a storage area of the non-volatile memory through data lines, wherein the controller transmits a command through the data lines to access the storage area of the non-volatile memory. The command is further returned from the non-volatile memory to the controller through the data lines for comparison, to determine whether the command is correctly received by the non-volatile memory.

Abstract: A storage application may provide protection of data accesses by clients without incurring metadata storage costs. A request to store a record may be received, where subsequent accesses to the stored data are protected by an access condition that includes a key or other metadata. To store the record, a composite record including the record and the security key may be generated and a detection code may be determined for the composite record. The record may then be stored along with the detection code. A request to access the record may then be received, the access request including an access key. The record and detection code may be retrieved and a new composite record including the retrieved record and the access key may be generated. Satisfaction of the access condition may be determined according to a new detection code generated from the new composite record.

Abstract: Systems and methods are provided for intercepting computing requests and modifying the execution timing thereof based on thresholds and minimum performance criteria and/or adjusting hosted services plans in order to monitor and control costs of hosting software applications on hosted provider computing resources.

Abstract: Methods that may be performed by a host controller and a memory controller of a computing device. The method synchronizes memory tables between the storage device and a host device by modifying an indicator in a first memory table on the storage device in response to a change in a memory mapping, the first memory table mapping logical addresses to physical addresses of memory on the storage device, the indicator identifying one or more address mapping changes of the first memory table, notifying the host device that the first memory table has been modified, and transmitting to the host device at least a portion of the first memory table including the one or more address mapping changes. The storage device processes memory requests from the host device based on one or more addresses affected by the one or more address mapping changes.

Abstract: The disclosure herein describes deduplicating data chunks using chunk objects. A batch of data chunks is obtained from an original data object and a hash value is calculated for each data chunk. A first duplicate data chunk is identified using the hash value and a hash map. A chunk logical block address (LBA) of a chunk object is assigned to the duplicate data chunk. Payload data of the duplicate data chunk is migrated from the original data object to the chunk object, and a chunk map is updated to map the chunk LBA to a physical sector address (PSA) of the migrated payload data on the chunk object. A hash entry is updated to map to the chunk object and the chunk LBA. An address map of the original data object is updated to map an LBA of the duplicate data chunk to the chunk object and the chunk LBA.

Abstract: In an example, a non-transitory computer-readable storage medium storing instructions that, when executed by a processor of a computing device, cause the processor to maintain, via execution of a write filter executable on the computing device, an overlay region for a protected volume, the overlay region having a first size that occupies a portion of a system memory. Further, the processor may retrieve historical data that describes past behavior of the computing device with respect to the overlay region and a non-overlay region of the system memory. Furthermore, the processor may determine a second size for the overlay region based on the historical data. Prior to a boot of the computing device, the processor may store an instruction to modify the first size of the overlay region in accordance with the determined second size.

Abstract: A circuit includes one or more datastores configured to store a result register and a readout counter value and logic circuitry coupled to the one or more datastores. The logic circuitry is configured to cause, for a cycle of a plurality of cycles of a periodic signal, one or more analog-to-digital converters (ADCs) to store data to the result register and modify the readout counter value in response to the one or more ADCs storing the data to the result register for the cycle. In response to a read request for the data at the result register for the cycle, the logic circuitry is configured to output the data stored by the result register, output the readout counter value for the cycle, and, after the output of the readout counter value, set the readout counter value to a predetermined value.

Abstract: A method of continuous data protection (CDP) is provided. The method includes sending, by a splitter, block I/O write data from a computing system to a primary volume and to a CDP appliance. The method further includes, recording, by a file system tracker communicatively coupled with the splitter, a log of meta data operations made to files in a file system of the primary volume and sending the log to the CDP appliance. The method further includes, recording, by the CDP appliance, the block I/O write data in a journal and a secondary volume, and recording the log of meta data operations made to files in the file system of the primary volume in a continuous catalog.

Abstract: A system analyzes data associated with a failure of an information handling system by evaluating memory addresses found in memory, such as bug check parameters, context register values, or stacks in a memory dump, at the time of a fatal error to determine whether one of the memory addresses has a single-bit error, and modifying a first memory address with the single-bit error to generate a second memory address, wherein the first memory address is one of the memory addresses being evaluated. If a second memory address is mapped to the page table, the system authorizes a repair of the information handling system.

Abstract: A throttling method for a storage device is provided. The throttling method includes: receiving a write command from a host; identifying, using a first machine learning model, a throttling delay time; transmitting a completion message to the host according to the throttling delay time; collecting weights of the first machine learning model and performance information of the storage device corresponding to the weights; learning the weights and the performance information to generate an objective function indicating a relationship between the weights and the performance information using a second machine learning model of a weight learning device; selecting a weight corresponding to a maximum performance using the objective function; and updating the first machine learning model with the weight.

Abstract: A network isolation device includes an internal network interface to connect the network isolation device to an internal network and an external network interface to connect the network isolation device to an external network. The network isolation device further includes an airgap device that operates to (i) close an air gap to connect the internal network to the external network, (ii) open the air gap to disconnect the internal network from the external network. The device further includes a signal receiver that receives a signal from a signal source, and based on the signal, performs an authentication process to determine whether the signal or the signal source are authorized. In response to determining that the signal or the signal source is authorized, the receiver operates the airgap device to close the air gap and connect the internal network to the external network.

Abstract: A cache may store critical cache lines and non-critical cache lines, and may attempt to retain critical cache lines in the cache by, for example, favoring the critical cache lines in replacement data updates. Multiple levels of criticality may be available for a given cache line and cache circuitry may adjust the criticality value of in response to a criticality event. One or more upper criticality levels may be masked when selecting a victim cache line for replacement.

Abstract: Methods, systems, and devices for configurable types of write operations are described. A memory device may receive a write command to write data in a zone of a memory system. The memory device may identify a physical address to store the data using a cursor associated with the zone based at least in part on receiving the write command. In some examples, the cursor may be associated with a type of a write operation based on a quantity of data associated with the cursor. As such, the memory device write, using a first type of the write operation or a second type of the write operation in accordance with the quantity of data, the data, and an indication of the type of the write operation used to write the data into the memory system.

Abstract: Exemplary methods, apparatuses, and systems include detecting an operation to write dirty data to a cache. The cache is divided into a plurality of channels. In response to the operation, the dirty data is written to a first cache line in the cache, the first cache line being accessed via a first channel. Additionally, a redundant copy of the dirty data is written to a second cache line in the cache. The second cache line serves as a redundant write buffer and is accessed via a second channel, the first and second channels differing from one another. A metadata entry for the second cache line is updated to reference a location of the dirty data in the first cache line.

Abstract: Techniques are provided for implementing a persistent memory storage tier to manage persistent memory of a node. The persistent memory is managed by the persistent memory storage tier at a higher level within a storage operating system storage stack than a level at which a storage file system of the node is managed. The persistent memory storage tier intercepts an operation targeting the storage file system. The persistent memory storage tier retargets the operation from targeting the storage file system to targeting the persistent memory. The operation is transmitted to the persistent memory.

Abstract: Processing functions are offloaded to a memory controller for nonvolatile memory by a host in connection with write data. The nonvolatile memory executes these functions, producing processed data that must be written into memory; for example, the offloaded functions can include erasure coding, with the nonvolatile memory controller generating redundancy information that must be written into memory. The memory controller holds this information in internal RAM and then later writes this information into nonvolatile memory according to dynamically determined write time and/or destinations selected by the host, so as to not collide with host data access requests. In one embodiment, the memory is NAND flash memory and the memory controller is a cooperative memory controller that permits the host to schedule concurrent operations in respective, configurable virtual block devices which have been configured by the host out of a pool of structural flash memory structures managed by the memory controller.