Patents Examined by Masud K Khan
  • Patent number: 12379860
    Abstract: A front-end firmware component of a memory sub-system receives a first request to perform a first set of initialization operations and initiates a first set of initialization operations for the front-end component in parallel with initiating a second set of initialization operations for a back-end component. Responsive to completing the first set of initialization operations, the front-end component sends a first notification to a host computer system to indicate that the front-end component is available to respond to requests for configuration data associated with the memory sub-system, receives a second request from the host computer system for a configuration data associated with the memory sub-system, and responsive to receiving the second request from the host computer system before the back-end component has completed the second set of initialization operations, provides the configuration data to the host computer system.
    Type: Grant
    Filed: April 4, 2024
    Date of Patent: August 5, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Ximin Shan, Venkata Naga Lakshman Pasala, Noorshaheen Mavungal Noorudheen
  • Patent number: 12373120
    Abstract: The disclosure provides a method, a distributed controller and a system for managing sequential storage devices in a distributed storage environment. The method comprising receiving a client allocation request from a client device and determining at least one zone set from a plurality of zone set based on the client allocation request and predefined I/O parameters. Each zone set of the plurality of zone set comprises a plurality of zones of sequential storage devices. Thereafter, method comprises provisioning the at least one zone set to the client device based on the client allocation request, thereby, managing the sequential storage devices. Each zone of a sequential storage device is arranged into a zone set based on at least one of sequential storage device parameters, and zone parameters. The use of the distributed controller allows optimizing the performance of the sequential storage devices and optimizing the network bandwidth utilization.
    Type: Grant
    Filed: March 27, 2023
    Date of Patent: July 29, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Arun George
  • Patent number: 12366972
    Abstract: A method for rebuilding data when changing erase block sizes in a storage system is provided. The method includes determining one or more erase blocks to be rebuilt and allocating one or more replacement erase blocks, wherein the one or more erase blocks and the one or more replacement erase blocks have differing erase block sizes. The method includes mapping logical addresses, for the one or more erase blocks, to the one or more replacement erase blocks and rebuilding the one or more erase blocks into the one or more replacement erase blocks, in accordance with the mapping.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: July 22, 2025
    Assignee: PURE STORAGE, INC.
    Inventors: Andrew R. Bernat, Timothy W. Brennan, Mark L. McAuliffe, Neil Buda Vachharajani
  • Patent number: 12367156
    Abstract: A logical-to-physical (L2P) data structure comprising a plurality of L2P table entries is maintained on the volatile memory device. Each L2P table entry comprises a block number and a page table index corresponding to the non-volatile memory device. A plurality of physical-to-logical (P2L) data structures each comprising a plurality of P2L table entries is maintained on the volatile memory device. Each of the plurality of P2L data structures corresponds to a portion of the L2P data structure.
    Type: Grant
    Filed: February 21, 2024
    Date of Patent: July 22, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Meng Wei
  • Patent number: 12366982
    Abstract: Techniques are provided for data management across a persistent memory tier and a file system tier. A block within a persistent memory tier of a node is determined to have up-to-date data compared to a corresponding block within a file system tier of the node. The corresponding block may be marked as a dirty block within the file system tier. Location information of a location of the block within the persistent memory tier is encoded into a container associated with the corresponding block. In response to receiving a read operation, the location information is obtained from the container. The up-to-date data is retrieved from the block within the persistent memory tier using the location information for processing the read operation.
    Type: Grant
    Filed: December 28, 2023
    Date of Patent: July 22, 2025
    Assignee: NetApp, Inc.
    Inventors: Ananthan Subramanian, Matthew Fontaine Curtis-Maury, Ram Kesavan, Vinay Devadas
  • Patent number: 12360707
    Abstract: A data storage technique involves determining one or more storage allocation units from a virtual storage region corresponding to a disk set including a plurality of disks. The technique further involves allocating a virtual storage unit to the one or more storage allocation units. The technique further involves storing a mapping relationship of the virtual storage unit with respect to the virtual storage region and the one or more storage allocation units. Accordingly, the granularity of each virtual storage unit can be reduced, so that storage resources can be invoked more accurately, and the storage space can be saved.
    Type: Grant
    Filed: July 13, 2023
    Date of Patent: July 15, 2025
    Assignee: Dell Products L.P.
    Inventors: Hongpo Gao, Jamin Kang, Jian Gao
  • Patent number: 12360665
    Abstract: An operating method of a storage device, including a core and a memory, includes receiving a first processing code configured to enable execution of a first task and storing the first processing code in a first logical unit separately allocated in the memory for near-data processing (NDP), in response to a write command received from a host device, activating the core for executing the first processing code, in response to an activation command received from the host device, and executing the first task by using the core, in response to an execution command received from the host device.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: July 15, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngmin Lee, Changjun Lee, Jinmyung Yoon, Gyuseok Choe, Seongwan Hong
  • Patent number: 12353321
    Abstract: Content describing an intended usage of a storage system is received. The content is analyzed by a generative artificial intelligence (AI) model to identify the intended usage described by the content. One or more configurations of the storage system are identified that support the intended usage described by the content. A response including the one or more configurations of the storage system is generated.
    Type: Grant
    Filed: October 3, 2023
    Date of Patent: July 8, 2025
    Assignee: PURE STORAGE, INC.
    Inventor: Rohit Gottiparthy
  • Patent number: 12353732
    Abstract: A storage device of the present disclosure includes a memory device including a system memory storing system information used in an operation, and a register storing a register value indicating that the system information is a first state or a second state, and a memory controller configured to control the memory device to receive the register value from the memory device when power is turned on, and to initialize the system information stored in the system memory when the received register value indicates that the system information is the first state.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: July 8, 2025
    Assignee: SK hynix Inc.
    Inventor: Ho Ryong You
  • Patent number: 12339784
    Abstract: An apparatus for cache management includes an interface and a processor. The interface is for communicating with a cache memory configured to store data items. The cache controller is configured to obtain a classification of the data items into a plurality of groups, to obtain respective target capacities for at least some of the groups, each target capacity defining a respective required size of a portion of the cache memory that is permitted to be occupied by the data items belonging to the group, and to cache new data items in the cache memory, or evict cached data items from the cache memory, in accordance with a policy that complies with the target capacities specified for the groups.
    Type: Grant
    Filed: August 14, 2022
    Date of Patent: June 24, 2025
    Assignee: Mellanox Technologies, Ltd
    Inventors: Gal Yefet, Yamin Friedman, Daniil Provotorov, Ariel Shahar, Natan Oppenheimer, Ran Avraham Koren, Avi Urman
  • Patent number: 12332788
    Abstract: Embodiments of the present disclosure relate to a system and an operating method of the system. Based on some embodiments of the disclosed technology, the system may include a random access memory structured to include memory cells to store data, a cache memory configured to cache at least part of the data, and a processor in communication with the random access memory and the cache memory to access at least part of the data from the random access memory or cache memory. The system may determine a cache hit ratio for the cache memory, and may set an operating frequency of the random access memory based on the cache hit ratio.
    Type: Grant
    Filed: January 19, 2024
    Date of Patent: June 17, 2025
    Assignee: SK HYNIX INC.
    Inventors: Yong Wan Hwang, Nam Hyeok Jeong, Kwang Ho Choi, Moon Hyeok Choi, Tae Woong Ha
  • Patent number: 12321272
    Abstract: A buffer of a processing system allows younger stores to write to a data cache before an older store completes its write operation to the data cache while maintaining the appearance of committing stores in program order. To maintain the appearance that a blocked store completed its write operation to the data cache, the processing system cancels the blocked store while “locking” the cache line in the data cache in an exclusive state to which the blocked store is attempting to write. The data cache negatively acknowledges any probes to the cache line until the blocked store has completed the write operation. The buffer thus decouples completing the write operation from global observability of the write operation.
    Type: Grant
    Filed: March 28, 2023
    Date of Patent: June 3, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventor: John M. King
  • Patent number: 12321273
    Abstract: Cascading execution of atomic operations, including: receiving a request for each thread of a plurality of threads to perform an atomic operation, wherein the plurality of threads comprises a plurality of thread subsets each corresponding to a local memory, wherein the local memory for a thread subset is accessible by the thread subset and inaccessible to a remainder of threads in the plurality of threads; generating a plurality of intermediate results by performing, by each thread subset, the atomic operation in the local memory corresponding to the thread subset; and generating a result for the request by aggregating the plurality of intermediate results in a shared memory accessible to all threads in the plurality of threads.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: June 3, 2025
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Jimshed Mirza, Mark Fowler
  • Patent number: 12314161
    Abstract: A method and an apparatus for controlling read timing, and a computer-readable storage medium. The apparatus for controlling read timing includes an on-chip memory. The method for controlling read timing includes: writing input data into the on-chip memory; performing an end-of-frame detection on the input data; after detecting an end of a frame, counting input data rows and generating a read timing according to a preset Porch parameter; determining whether the on-chip memory will be read to be empty or written to be full according to an input data row count and the generated read timing; and when the on-chip memory will be read to be empty or written to be full, adjusting the read timing until the on-chip memory will not be read to be empty or written to be full, and reading and outputting data of the on-chip memory according to the read timing.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: May 27, 2025
    Assignees: Chongqing BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Wentao Zhu, Gaoming Sun, Jingchao Yuan, Zhiheng Zhou, Hongxin Pan, Jingpeng Zhao, Xin Duan
  • Patent number: 12299322
    Abstract: Methods, systems, and devices for an elastic buffer for a media management operation are described. A plurality of entries associated with a media management operation for a memory sub-system are stored. A first set of one or more write commands associated with the media management operation are buffered using the plurality of entries based on a second set of one or more write commands associated with a host write procedure. The first set of one or more write commands associated with the media management operation are issued based on the plurality of entries and a completion of the second set of one or more write commands associated with the host write procedure.
    Type: Grant
    Filed: October 26, 2022
    Date of Patent: May 13, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Antonio David Bianco
  • Patent number: 12293111
    Abstract: A method of using flash storage devices with different sized erase blocks is provided. The method includes allocating a plurality of erase blocks of heterogeneous erase block sizes to a RAID stripe, to form a tile pattern having the heterogeneous erase block sizes in the RAID stripe. The method includes writing the RAID stripe across the flash storage devices in accordance with the allocating, and stopping the writing the RAID stripe, responsive to contents of the RAID stripe reaching a threshold.
    Type: Grant
    Filed: July 13, 2023
    Date of Patent: May 6, 2025
    Assignee: PURE STORAGE, INC.
    Inventors: Eric D. Seppanen, Andrew R. Bernat, Timothy W. Brennan, Mark L McAuliffe, Neil Buda Vachharajani
  • Patent number: 12293082
    Abstract: Provided is a computer system capable of maintaining a storage capacity allocated to a journal volume within an appropriate range during an application period of remote copy. A first storage system includes a primary volume and a primary journal volume, and a second storage system includes a secondary volume and a secondary journal volume. A management computer is configured to manage the remote copy in which a primary volume, a primary journal volume, a secondary journal volume, and a secondary volume are paired, and expand and/or release a capacity of the primary journal volume and/or the secondary journal volume according to operation information of a resource related to the remote copy.
    Type: Grant
    Filed: August 30, 2023
    Date of Patent: May 6, 2025
    Assignee: HITACHI VANTARA, LTD.
    Inventors: Tsukasa Shibayama, Akira Deguchi
  • Patent number: 12293094
    Abstract: A method includes sending an enumeration of a resource unit of the computing device to a first computing system tenant and to a second computing system tenant. The enumeration is sent through a first protocol and indicating a managing protocol associated with managing the resource unit. The method further includes receiving a first request from the first computing system tenant to reserve the resource unit. The first request is received through the managing protocol. The method further includes receiving a second request from the second computing system tenant to reserve the resource unit. The second request is received through the managing protocol. The method further includes sending, to the second computing system tenant, an indication that the resource unit is reserved by the first computing system tenant. The indication is sent through the managing protocol.
    Type: Grant
    Filed: January 3, 2024
    Date of Patent: May 6, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Daniel Lee Helmick
  • Patent number: 12293081
    Abstract: The present disclosure relates to field of Dual In-Line Memory Modules that discloses method and system for generating memory maps. The method comprises detecting, by computing system, at least one of DIMM and one or more Dynamic Random Access Memory (DRAM) chips associated with computing system. The one or more accelerators are configured in at least one of DIMM and one or more DRAM chips. Further, the method includes determining accelerator information for each of one or more accelerators via at least one of Serial Presence Detect (SPD) and Multi-Purpose Register (MPR) associated with at least one of DIMM and one or more DRAM chips. Method includes generating unique memory map for each of one or more accelerators based on accelerator information of corresponding one or more accelerators. As a result, performance of computing system may be improved as accelerator capabilities of one or more accelerators are effectively utilized.
    Type: Grant
    Filed: May 2, 2023
    Date of Patent: May 6, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Raghu Vamsi Krishna Talanki, Archita Khare, Eldho P. Mathew, Jin In So, Jong-Geon Lee, Venkata Ravi Shankar Jonnalagadda, Vishnu Charan Thummala
  • Patent number: 12287988
    Abstract: A technique for accurate communication between a non-volatile memory and its controller. The controller accesses a storage area of the non-volatile memory through data lines, wherein the controller transmits a command through the data lines to access the storage area of the non-volatile memory. The command is further returned from the non-volatile memory to the controller through the data lines for comparison, to determine whether the command is correctly received by the non-volatile memory.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: April 29, 2025
    Assignee: SILICON MOTION, INC.
    Inventors: Hsu-Ping Ou, Chien-Hung Lee