Abstract: An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.

Abstract: A method of processing memory, suitable for loading an executable object code compiled from a source code into the memory that includes defective memory cells. At first, set up a plurality of pre-compiled object codes that correspond to a source code, each pre-compiled object code having at least a skipped-code-address range. Then, test the memory and locate the defective addresses therein. According to the result of the test, the code-loading system selects an executable object that has the matching skipped-code-address range from the pre-compiled object codes, and loads the executable code into the memory. Since the skipped-code-address range covers the defective addresses in the memory, the defective memory cells in the memory won't affect the operation of loading a program.

Abstract: Aspects for increasing yield in an embedded memory device are described. With the aspects of the present invention, a cache is provided for a memory unit of an embedded memory device. Attempts to access a failed bit memory location in the memory unit are determined. When a failed memory bit location is being accessed, substitution of a memory location in the cache for the failed bit memory location occurs.

Abstract: A can test interface system and method provides an interface between upstream scan test devices and downstream scan test devices. In one embodiment, the present invention utilizes a scan test interface comprising a scan interface chip (SIC) that facilitates a flexibly programmable system level scan test architecture. The SIC includes a scan test interface register, a system interface, a scan test interface controller, a board interface and a selection circuit.

Abstract: A semiconductor device includes a first circuit and a second circuit cascaded therefrom, a pattern examination section for examining the input signal pattern for the first circuit to estimate a delay in the first circuit, a delay control block for controlling an internal source potential based on the estimated delay for controlling the source potential for the second circuit so that the signal delay from the second circuit has small variations of delay time. The integrated circuit can be formed on a reasonable specification, and achieves a lower dissipation and a higher reliability.

Abstract: A mechanism for providing error protection for data that is to be stored in a data storage system in which data are stored in data sectors in a data storage area and redundant information that provides error protection for the data are stored in redundant sectors in a redundant storage area. New data that is written to a designated one of the data sectors, and that is not error protected by the redundant information, is received, and error correction information for the new data is selectively stored in an additional storage area to provide error protection for the new data instead of revising the redundant information to provide such error protection.

Abstract: A scan test interface system and method provides an interface between upstream scan test devices and downstream scan test devices. The scan test interface system and method receives scan test signals, facilitates flexible configuration of scan test signals and transmits scan test signals on subordinate scan test chains. A scan test interface includes a scan test interface register, a system interface, a scan test interface controller, a board interface and a selection circuit.

Abstract: A scan test interface system and method provides an interface between upstream scan test devices and downstream scan test devices. In one embodiment, the present invention utilizes a scan test interface comprising a scan interface chip (SIC) that facilitates a flexibly programmable system level scan test architecture. The SIC includes a scan test interface register, a system interface, a scan test interface controller, a board interface and a selection circuit.

Abstract: Synchronous dynamic random access memory (SDRAM) method and apparatus are provided for implementing address error detection. Addressing errors are detected on the memory interface independent of data ECC, with reduced memory read access latency and improved processor performance. Addressing errors are detected while allowing differentiation between memory addressing failures that are required to stop the system and memory cell failures that allow continued operation. A predefined pattern is generated for a write burst to the SDRAM. The predefined pattern is dependent on a write address. A bit of the predefined pattern is sequentially stored into the SDRAM on each burst transfer of the write burst to the SDRAM. An expected pattern is generated from a read address for a read burst. The stored predefined pattern is retrieved during a read burst. The retrieved predefined pattern is compared to the generated expected pattern for identifying a type of an addressing error.

Abstract: To improve the processing efficiency and throughput by performing only a recovery process in read-accessing to a memory even when an address parity error has occurred in write-accessing to the memory, a selector is provided to select one of write data and a parity-bitted address for writing to the memory. If an address parity error has detected, the selector selects the parity-bitted address, in which the address parity error has occurred, instead of write data to be written to the memory during the write-accessing thereto. This address parity error processing method is particularly useful when applied to an information processor, such as a computer system, including a storage (memory).

Abstract: A system for testing a memory page of a computer while an operating system is active. The system includes a hook function and a pattern generator. The hook function has software instructions that takes the place of a memory allocation/release scheme of the operating system. The system stores a test pattern generated by the pattern generator in the memory page upon receiving a request to release the memory page. Upon receiving a request to allocate the memory page, the system verifies the test pattern is correct to ensure the memory page is not defective. If the test pattern is incorrect, the defective memory page is removed from service.

Abstract: A clock adjusting method adjusts a first clock supplied to a first flip-flop which is coupled to an output of a first circuit and a second clock supplied to a second flip-flop which is coupled to an input of a second circuit, where the first and second flip-flops are coupled via a transmission path. The clock adjusting method includes the steps of (a) transmitting data from the first flip-flop to the second flip-flop via the transmission path while varying delay quantities of the first and second clocks, (b) obtaining a combination of the delay quantities of the first and second clocks with which the data is correctly transmitted from the first flip-flop to the second flip-flop, and (c) adjusting the delay quantity of at least one of the first and second clocks based on the combination so as to synchronize operations of the first and second flip-flops.

Abstract: A method and apparatus for providing the header checksum of a data packet.

Abstract: The present invention discloses an embedded and test mode timer circuit that is used to perform operations in an embedded mode and a plurality of test modes in a memory device. When the memory device is operating in the embedded mode, the embedded and test mode timer circuit is activated to automatically direct at least one logic circuit to execute logic tasks at predetermined times. When the memory device is operating in a test mode, the embedded and test mode timer circuit is activated to automatically direct a portion of the logic circuits to execute logic tasks at predetermined times and the remaining portion of the logic circuit are manually directed.

Abstract: The present invention includes alternative methods for selecting forward error correction parameters to be used in multi channel communications. Method embodying aspects of the present invention may include acquiring signal to noise ratio data for a set of communications channels, counting, estimating or identifying channels to carry data, computing an average signal to noise ratio for channels used and selecting set(s) of FEC parameters. It may predicting net SNR gains and storing these predictions as splines or in interpolation tables. This invention is specifically applicable to Reed-Solomon encoding for FEC and selecting the Reed-Solomon parameters S and R/S. Symbol sets, represented by S may consist of dmt symbols or of data carried by multiple channels in one transmission interval. The computations for selecting parameters may include adjusting the average signal to noise ratio by a safety margin.

Abstract: A device for generating L addresses, which are smaller in number than 2m×Ng virtual addresses, for reading data from an interleaver memory in which L data bits are stored, the device including: Ng PN generators each including m memories; an address generator for adding an offset value to the input data size to provide a virtual address having a size of a multiple of 2m, and generating addresses other than addresses corresponding to the offset value in address generation areas using the address generation areas having the size of 2m; and means for reading the input data from the interleaver memory using the addresses generated from the address generation areas.

Abstract: A method for testing a semiconductor memory device according to one embodiment comprises the steps of: checking data in all addresses of the semiconductor memory device for correctness in-units of m×n bits: ending if it is determined that data in all the semiconductor memory device; if there is a defective address, comparing each m-bit data constituting the (m×n)-bit data corresponding to the defective address with its expected value; and if the comparison result indicates that the m-bit data is erroneous, determining whether the defective semiconductor memory device can be repaired. Due to this step, man hours required for testing a semiconductor memory device having a wide data bus of an (m×n)-bit width can be considerably reduced.

Abstract: A test system includes a semiconductor device having a circuit configuration including an input buffer circuit, an output buffer circuit, and an internal logic, a random data generation circuit being provided at the front stage of the output buffer circuit; a random data generator, incorporating a random data generation circuit, for applying a random data to an input of the input buffer circuit from the random data generation circuit; and a test board on which the semiconductor device and random data generator is mounted and electrically connected to each other.

Abstract: Multiple verification cases consisting of code sequence and initial context, and suitable for electrical verification testing of a device, are generated from a single verification case by permuting, or changing, the code sequence, by either permuting the initial context of the code sequence or permuting the code sequence itself. The code sequence is an array of computer instructions to be executed by a computer and the initial context of the code sequence refers to the environment in which the code sequence is to be run.

Abstract: A method for utilizing an XOR network for testing internal nodes of a die wherein the nodes are connected to the input ports of the XOR network. The nodes are chosen by an iterative algorithm whereby the toggled, but not observed nodes, are partitioned into subsets belonging to a test hierarchy whereby the largest subset in the hierarchy is chosen. Based upon this largest subset, a first and second node set is constructed. A functional test is performed wherein the first and second node set, respectively, are inputs and outputs. The second node set serves as inputs to the XOR network. Deeper levels of hierarchies are created if the functional test on the first an second node sets do not meet a fault coverage criterion, or if the hierarchy level is too large, where the deeper test hierarchy is constructed from the largest subset associated with a less deep hierarchy.