Abstract: The present invention provides an error correction apparatus and an error correction method, which does not execute unnecessary syndrome operation and operation processing subsequent to the syndrome operation. A format interface 10a judges whether an uncorrectable error is included in parallel with demodulation of received data, and outputs an error correction incapability detection signal when the uncorrectable error is included. The error correction circuit 20a executes decoding of the error correction, including syndrome operation, for demodulated data from the format interface 10a, suspends the syndrome operation when the error correction incapability detection signal is input, and terminates the error correction.

Abstract: A continuity test mode circuit in an integrated circuit device having a means for switching between a continuity test mode and a normal operating mode. The test mode is characterized by one or more input pins being in direct electrical connection with one or more output pins to enable the pins and the chip packaging and chip socket and circuit board to be tested for continuity. In normal operating mode, the operation of the chip is not affected by the test mode circuitry. The continuity test mode circuit allows for testing of device-socket and/or device-board continuity in order to ensure accurate testing and programming of the device.

Abstract: A method of error correction during a soft handover process is disclosed wherein a radio network control node receives a plurality of versions of the same data block. Two or more of the received versions of the data block are combined to determine a substantially error corrected version of the data block. The resulting substantially error corrected version of the data block may then be forwarded to to other network nodes.

Abstract: A test device for electrically testing an electronic device (DUT) 100 comprises a pattern memory 13A, a pattern generator 13, a first filter 20B, and a pin electronic assembly 19. The pattern memory 13A stores data defining test patterns to be supplied to the DUT 100. The pattern generator 13 generates a plurality of test patterns to be input to a plurality of input pins of the DUT using digital signals based on the data stored in the pattern memory 13A. The first filter converts at least one of the plurality of test patterns to analog signals. The pin electronic assembly 19 supplies the plurality of test patterns including the analog signal test pattern to the DUT 100.

Abstract: A memory fault analyzer having a comparator and fault analyzer storage is disclosed along with a method of testing faults of the memory using a built in fault analyzer. The memory is tested by writing a known data onto a bit, reading the bit for stored data, comparing the known data with the stored data, and storing address of faulty bits in the fault analyzer. Because the fault analyzer is built in with the memory, the process is very fast. And, the fault analyzer may count the number of rows and the number of columns requiring replacement, compare the counted numbers with the number of available redundant rows and columns, and generate a repairability signal.

Abstract: An anlog boundary scan compliant integrated circuit system carries out a test more reliably and cuts down on power dissipated during normal operation. To perform a test of whether or not an interconnect is connected normally between integrated circuits, multiple logic circuits with mutually different input threshold voltages are provided to detect the logical level of a potential at a terminal, thereby improving the reliability of the test. Potential fixers and power isolators are optionally provided. During normal operation, the power fixers fix the output potentials of the logic circuits, while the power isolators electrically isolate the logic circuits from the ground. As a result, no current flows through the logic circuits or other circuits in succeeding stages while no tests are carried out.

Abstract: An internal memory in an ASIC device which is capable of allowing timing constraints to control signals in an asynchronous two-port RAM is disclosed. The present internal memory includes delays which synchronizes the timing of the read and write signals. Also, a method for easily and accurately testing a two-port RAM is disclosed, allowing a stable implementation of an internal memory in an ASIC device.

Abstract: A coding device includes a coding circuit for converting a digital input into a coded output having a greater number of bits than the input, an interleaving circuit for combining a plurality of words of the coded output and producing therefrom a data block having a plurality of the interleaved words, and a puncturing circuit or repeating circuit for puncturing or repeating bits from the data block. The puncturing or repeating circuit uses a deleting or repeating pattern to provide data words for transmission during respective frames of a transmission channel. The deleting or repeating pattern is selected depending upon the characteristics of the coding circuit and of the interleaving circuit. The coding device is for use in a cordless communication system.

Abstract: A semiconductor device which has a test mode for testing the semiconductor device, is provided with a circuit which generates a first signal based on dummy command signals which are input thereto a plurality of times, and generates a second signal which instructs entry to a corresponding test mode or an exit from a corresponding test mode based on an address signal and the first signal.

Abstract: A clock adjusting method adjusts a first clock supplied to a first flip-flop which is coupled to an output of a first circuit and a second clock supplied to a second flip-flop which is coupled to an input of a second circuit, where the first and second flip-flops are coupled via a transmission path. The clock adjusting method includes the steps of (a) transmitting data from the first flip-flop to the second flip-flop via the transmission path while varying delay quantities of the first and second clocks, (b) obtaining a combination of the delay quantities of the first and second clocks with which the data is correctly transmitted from the first flip-flop to the second flip-flop, and (c) adjusting the delay quantity of at least one of the first and second clocks based on the combination so as to synchronize operations of the first and second flip-flops.

Abstract: A fault tolerant integrated circuit employs triple redundant storage of data and continuous voting to protect the data from Single Event Upset, or SEU. The integrated circuit includes three or more registers and a majority voter. The three registers are connected in series to each other with the output of the first register being connected to the input of the second register and the output of the second register being connected to the input of the third register. The majority voter is connected to the output of each register and generates a signal corresponding to the majority of all of the register outputs. The output of the majority voter is connected to the input of the first register, thereby correcting any incorrect data stored in the registers.

Abstract: A multicast communication system for small groups using a protocol to indicate to routers receiving a packet according to the protocol to perform the following process: (1) determining a next hop for each of the destination nodes listed in the packet received; (2) partitioning the destination nodes into groups according to the next hop determined for each destination node in the preceding step; (3) replicating the packet such that there is at least one copy of the packet for each of the next hops; (4) modifying the list of addresses for the destination nodes such that the list of addresses for each of the next hops includes only the addresses for the destination nodes to be routed in that next hop; and (5) transmitting the modified copies of the packet to the next hops found in the previous steps for routing to the addresses included in each packet.

Abstract: A circuit comprising a phase detector/correction circuit, at least one column of memory cells, a control circuit and a sense amplifier. The control circuit may be configured to read a sequence from the memory cells in a predetermined order and present a first output signal. The sense amplifier may be configured to present a periodic signal in response to the first output signal.

Abstract: A decoding device for decoding an input codeword bit stream using a generator polynomial represented by the product of a plurality of sub-polynomials disclosed. The decoding device comprises a plurality of serial concatenated decoders each having different generator polynomials, wherein a product of the different generator polynomials becomes said generator polynomial, the different generator polynomials are represented by the different sub-polynomials or by a product thereof, and a first-stage decoder out of the serial concatenated decoders receives said codeword bit stream. The decoders each perform soft decision, and the codeword is a linear block code.

Abstract: A test bus architecture for testing an integrated circuit having a plurality of agents includes providing both a test block select signal and test function select signal to a plurality of select decoders respectively disposed in each of the plurality of agents. The test block select signal has a number of states at least equal to the number of agents and the test function select signal at least equal to a maximum number of internal signal groups of any one of the agents, each select decoder having at least one internal signal group which is outputted from circuitry to be tested within the agent of the select decoder. An output from each of the select decoders is fed to a test bus output such that a selected internal signal group is outputted to the test bus output upon the agent of the selected signal group being selected by the state of the test block select signal and the selected signal group being selected by the state of the test function select signal by the select decoder.

Abstract: Method and apparatus provides for testing a device or system with a pattern generator. A series of predetermined test vectors are stored, and, for at least some of the test vectors, an associated predetermined MISR signature. A test vector is applied to a device or system under test and a gold unit in response to a gating signal, the test vector having an associated MISR determined by simulating the expected result vector. In response thereto, the gold unit and the device or system under test each produce a result vector which are compared to detect errors in the performance of the system or device under test. A MISR signature is generated for the result vector from the gold unit. The MISR signature for the result vector is then compared to the MISR associated with the input test vector. If the signatures do not match, further test vectors are prevented from being applied to the device or system under test.

Abstract: A method providing integrity analysis of content data streams within an information distribution system. On-demand content is divided into a plurality of content portions to be severally distributed among disk drives of an array of disk drives. A data structure is used for dividing the content into the plurality of content portions. Method is used to check integrity of content prior to provisioning thereof.

Abstract: A semiconductor memory device is provided with an MPU, a secondary cache and a TAG memory mounted on a chip. Registers are provided for a plurality of test data buses connected parallel to a plurality of data buses from the MPU to the secondary cache or the TAG memory. The registers and the plurality of data buses of the MPU are changed with switches so as to be connected with a bonding pad which is a part of an external terminal for the MPU. With this arrangement, the semiconductor memory device can connect with a tester for a DRAM part test via the bonding pad.

Abstract: A programmable clock generator (220), which is part of an integrated circuit (IC) (210), provides clock signals (230) and (232) to various components of the IC. The clock generator includes a PLL (322) and one or more choppers (326, 328) which provide a desired waveform to the IC for testing purposes. When used in conjunction with a tester (212, 312), the IC can be scan tested at-speed using slower and less expensive testing equipment.

Abstract: Semiconductor device testing apparatus and method for testing a semiconductor device, includes: a pattern generator (10) which, based on a predetermined control sequence, generates an input signal pattern (12) and an expectation data signal pattern (14); a comparison unit (90) which compares an output signal pattern output from the semiconductor device and the expectation data signal pattern, and outputs a match signal when the output signal is matched with predetermined data determined based on the expectation data signal pattern. The pattern generator (10) includes: a stoppage unit which stops the control sequence when the match signal does not become active during a predetermined match cycle; a resuming address register which sets up a resuming address indicating a resuming position of the control sequence; and a resuming unit which resumes the control sequence based on the resuming address.