Abstract: A method for encoding data to meet a maximum run length limitation is disclosed. In one embodiment, the method comprises the steps of: (1) providing user data that includes a plurality of bits, wherein said bits have a value of 1 or 0; (2) performing an ECC computation on said plurality of user data bits to add ECC symbols in the form of a plurality of ECC bits; (3) randomizing the plurality of user data bits and said plurality of ECC bits; (4) analyzing said randomized user data bits and ECC bits to determine whether a number of consecutive bits have a common value; and, (5) inverting the value of a bit, when the number of consecutive bits having a common value exceeds the maximum run length limitation. Subsequently, representations of each of the randomized user bits and ECC bits, including any inverted bits, are stored onto a disk surface as magnetic-polarity transitions.

Abstract: Semiconductor device testers are provided which measure skew between two or more output pins of a semiconductor device independent of a strobe timing input. More particularly, a skew signal is generated by a comparator circuit that changes state when the respective outputs transition state, for example, from matching to differing states. In a two output pin embodiment, for instance, when one of the output pin changes state before the other and both initially are in the same state, a flip flop is set at the time when the data on the output pins first differs, i.e. when the first output pin transitions to a new state. The flip flop is then reset when the second output pin subsequently transitions to the new state and again matches the first output pin. The resulting duration of the output of the flip flop thereby corresponds to the time of skew of the output pins regardless of the initial state of the pins.

Abstract: An integrated circuit device is disclosed having a boundary scan chain and a hardwired BIST unit that is configurable via the control circuitry for the boundary scan chain. In one embodiment, the device includes application logic, a BIST unit, a boundary scan chain, a register, and a test access port. The application logic is the logic that provides the intended function of the chip. The BIST unit is configured to apply test patterns to the application logic to verify its functionality. The boundary scan chain is configured to sample input signals to the application logic and to control output signals from the application logic. The register stores an operational mode parameter for the BIST. The test access port provides external access to the boundary scan chain and the register, and is configured to control a clock signal to the BIST unit in accordance with the BIST operational mode parameter.

Abstract: According to one aspect of the present invention, a method is provided in which a device, in response to a read request issued by a host, transfers data to the host through a series of direct memory access (DMA) data in bursts. The host is allowed to interrupt the read command and determine whether a first portion has been transferred correctly from the device based upon an error code calculation transmitted from the device to the host during the termination phase of a data in burst.

Abstract: For the purpose of error masking, binary representation of parameter values are precoded at the transmitting end by a linear block code before transmission over a faulty channel, and the redundant information added in this way is not used at the receiving end for error detection within the binary parameter representations, but is utilized in the course of a parameter estimation to improve the quality of the estimated parameter values.

Abstract: A method for providing a compressed bit fail map, in accordance with the invention includes the steps of testing a semiconductor device to determine failed devices and transferring failure information to display a compressed bit map by designating areas of the bit map for corresponding failure locations on the semiconductor device. Failure classification is provided by designating shapes and dimensions of fail areas in the designated areas of the bit map such that the fail area shapes and dimensions indicate a fail type.

Abstract: The invention provides an initialization routine for digital signal processors that detects and maps out soft errors. A digital signal processing system may include an initialization routine stored in a non-volatile memory device that writes a bit pattern to the memory arrays. The routine may then cause the processor to perform refresh cycles to refresh the charge of each bit in the arrays. Next, the initialization routine may read data values from the memory arrays and compare them with the previously written bit pattern. If a value does not match the bit pattern, then the bit may have failed due to a soft error. An indication of the failed bit may then be stored in the first few rows of the memory array, thereby mapping out the failed location.

Abstract: The present invention involves a method for generating a partial Cyclic Redundancy Checking (CRC) value of a first interval of data in a digital data stream. The method includes the step of loading a precomputed CRC value corresponding to a one bit followed by a predetermined number of zeros. The predetermined number of zeros correspond to the number of digits of a polynomial minus one. The first interval of data is partitioned into a plurality of bits. The precomputed CRC value corresponding to the one bit followed by the predetermined number of zeros is enabled, for each of the plurality of bits having a value of one. The enabled, precomputed CRC values are combined to generate the partial CRC value of the first interval of data. Advantageously, multiple copies of the process may be executed in parallel to achieve a large speed-up.

Abstract: The present invention provides an encoding apparatus, comprising means (21) for generating a checksum for incoming data, means (22) for constructing frames on the basis of said incoming data and said generated checksum, and means (23) for multidimensionally coding said frames. Further, the present invention comprises a decoding apparatus for iterative decoding of multidimensionally decoded information, comprising means (28) for performing at least one decoding iteration on multidimensionally coded information, and means (32) for checking the decoded information after each decoding iteration and for causing said decoding iteration means (28) to perform a further decoding iteration on the basis of a checking result. The present invention further comprises the corresponding encoding method and decoding method. The average processing delay and the computational complexity is significantly reduced, since only the required number of iteration steps is adaptively performed in the decoding apparatus.

Abstract: The present invention provides a Reed-Solomon decoding apparatus comprising a device for monitoring occurrence of an error beyond an error correction capability and a degree of error correction. The Reed-Solomon decoding apparatus of the present invention comprises a Reed-Solomon decoder and a correction state monitor. The correction state monitor detects a process error in a Eucledean algorithm computer and a chain retrieval unit in the Reed-Solomon decoder, and generates a signal indicating the degree of error in input data.

Abstract: A timing system is disclosed that responds to pattern generation circuitry for producing test patterns for application to a device-under-test. The timing system includes a timing memory circuit that stores programmed edge timings for the patterns and couples to timing logic including a master oscillator and a plurality of fixed edge generators. The fixed edge generators are responsive to the programmed edge timings to produce the event timing signals.

Abstract: An error correction and detection system for a dual-pulse output metering device is provided. The system detects errors in the dual-pulse output of the metering device by comparing the current phase difference it between the pulse streams to a desired or known phase difference and generating an error signal if the current phase difference is different from the desired phase difference. If an error signal is generated, the system additionally accounts for the error and provides a corrected pulse count output by either discarding the extra pulse, or calculating the number of missed pulses, and adding the missing number of pulses to the pulse count output.

Abstract: An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.