Abstract: A flexible delay cell architecture and related methods are provided that may be used, for example, with input/output (I/O) blocks of a programmable logic device (PLD). In one implementation, a PLD includes a delay cell comprising a plurality of delay elements. The delay elements are adapted to delay an input signal to provide an output signal according to a delay setting corresponding to a number of the delay elements. The PLD also includes a register adapted to store the delay setting. The PLD further includes an edge monitor adapted to signal whether an edge transition of the output signal has occurred during a time window. In addition, the PLD includes logic adapted to adjust the delay setting stored by the register in response to the edge monitor signaling the edge transition.

Abstract: A semiconductor integrated circuit includes a digital circuit and a first-stage register circuit provided in a stage followed by the digital circuit. The digital circuit includes a logic circuit and a register circuit configured to temporarily retain a logic output from the logic circuit. The first-stage register circuit has a function as an alternative configured to test at least one register circuit and a function as an interface which supplies input data from an external input terminal to the digital circuit. The first-stage register circuit retains the input data from the external input terminal in synchronization with a clock signal, supplies the retained data to the digital circuit at the time of system operation, and outputs the retained data from an external output terminal connected to a dedicated output terminal or the digital circuit at the time of testing.

Abstract: A domino logic circuit includes an input circuit and an output circuit. The input circuit precharges a dynamic node at a first phase of a clock signal. The input circuit determines a logic level of the dynamic node by performing a logic evaluation of input data at a second phase of the clock signal. The output circuit is coupled between an output node and the dynamic node. The output circuit determines a logic level of the output node in response to the clock signal and the logic level of the dynamic node. The output circuit maintains the logic level of the output node while the logic evaluation is performed.

Abstract: A logic gate array is provided. The logic gate comprises a silicon substrate, a first logic gate layer on top of the silicon substrate, a second logic gate layer on top of the first logic gate layer, and a routing layer between the first and second logic gate layers for routing magnetic gates in the first and second logic gate layers, wherein the first logic gate layer, the second logic gate layer, and the routing layer are electrically connected by vias.

Abstract: The present invention relates to an antenna apparatus capable of multifrequency resonance and realizes downsizing and multifrequency resonance. The present invention relates to an antenna apparatus capable of multifrequency resonance or a radio communicating apparatus (e.g., portable phone) including the antenna apparatus; toward a feed element connected to and supplied with electricity from a feeding unit of a circuit substrate (printed circuit substrate), a non-feed element is disposed with over the circuit substrate or outside the circuit substrate; and the feed side or the open side of the feed element is electromagnetically coupled to the non-feed element to enable resonance in the frequency band of the non-feed element in addition to resonance in the frequency band of the feed element.

Abstract: A signal line 12 has at a first location a first driver 14 to drive a first signal level on that signal line 12. A second driver 16 is provided at a second location, separated from the first location, and serves to drive the line signal to a different value from that driven by the first driver 14. Associated with each of these drivers 14, 16 are respective keeper circuits 18, 20, 22; 24, 26, 28 serving to maintain the signal value driven by the respective remote driver 16; 14. Thus, the first keeper 18, 20, 22 local to the first driver 14 serves to maintain the signal value driven by the second driver 16. The keepers 18, 20, 22; 24, 26, 28 are disabled by the control signal which enables their local driver 14; 16 and thus do not contend with the change being driven by their local driver 14, 16.

Abstract: An impedance calibration period setting circuit includes a command decoder and an impedance calibration activation signal generator. The command decoder combines external signals to generate a refresh signal. The impedance calibration activation signal generator is configured to generate an impedance calibration activation signal in response to the refresh signal and an address signal. The impedance calibration period setting circuit prevents abnormal changes in an impedance calibration code and reduces current consumption.

Abstract: A mobile wireless communications device may include a portable housing, a circuit board carried by the portable housing and having a ground plane thereon, wireless communications circuitry carried by the circuit board, and an antenna assembly carried by the housing. More particularly, the antenna assembly may include a flexible substrate, an electrically conductive antenna element on the flexible substrate and connected to the wireless communications circuitry and the ground plane, and a floating, electrically conductive director element on the flexible substrate for directing a beam pattern of the antenna element.

Abstract: A programmable logic device having a Logic Element with an N-stage Look Up Table (LUT), dedicated hardware for performing a non-LUT logic function, and an over-ride element configured to selectively force a muxing stage within the N-stage LUT to select either one or more LUT configuration bit inputs or the output of the non-LUT logic function as the output of the LUT. In various embodiments, the non-LUT functions can include addition, subtraction, multiplication, division, digital signal processing, memory storage, etc.

Abstract: A source follower or emitter follower buffer provided according to an aspect of the present invention includes a capacitor connected between the input path and a node formed by the junction of a pair of transistors forming a cascoded current source connected to the output of the buffer. The capacitor passes input signal current directly to a switching load connected to the output of the buffer, and very little signal-dependant current flows through the transistor receiving the input signal. As a result, input-output non-linearity due to signal-dependant modulation (variation) of transconductance of the transistor receiving the input signal is minimized. When incorporated in switched-capacitor analog to digital converters, the buffer facilitates generation of digital codes that represent an input signal more accurately.

Abstract: A tristate buffer circuit includes a tristate buffer switchable into a high impedance state in response to configuration signal, a delay stage delays the an input signal to the tristate buffer and a gating stage having inputs for the input signal, a delayed input signal and an asynchronous tristate control signal and an output supplying the configuration signal to the tristate buffer. The gating stage sets the configuration signal to the high impedance mode only when the tristate control signal is set and the input signal and the delayed input signal have logic levels indicating that no signal transition of the input signal propagates within the delay stage. Depending upon signal polarity, the input signal and the delayed input signal are required to have the same digital state or opposite digital states.

Abstract: According to one aspect, an on-die termination (ODT) circuit is controlled during transition from a first power mode to a second power mode of a memory device. The transition from an asynchronous ODT circuit path to a synchronous ODT circuit path is delayed to compensate for an operational latency of a delay locked loop (DLL) circuit.

Abstract: A buffer circuit having an input terminal and an output terminal comprises a first inverter having an input node coupled to the input terminal and an output node coupled to the output terminal, a second inverter having an input node coupled to a reference voltage and an output node, a third inverter having an input node coupled to the output terminal and an output node coupled to the output node of the second inverter, a fourth inverter having an input node coupled to the output node of the second inverter and an output node coupled to the output terminal, a fifth inverter having an input node and an output node coupled to the output terminal, a sixth inverter having an input node and an output node coupled to the output node of the second inverter, a first resistive element is coupled between the output terminal and the input node of the fifth inverter, and a second resistive element is coupled between the output node of the second inverter and the input node of the sixth inverter.

Abstract: Reducing power consumption in latches and similar electronic devices. In one aspect, an apparatus for configuring power consumption of sequential logic includes a sequential logic device including a first latch, a second latch, and first and second enable inputs. The first enable input enables and disables the first and second latches, and the second enable input enables and disables the second latch and does not affect the first latch. The first enable input has an earlier required signal arrival time than the second enable input to be effective for a particular clock cycle. A circuit configures the sequential logic device at operating time to consume less power during a lower frequency of operation of the sequential logic device, and to consume more power during a higher frequency of operation.

Abstract: An integrated circuit including a digital key provider comprising an output and an enable-input, wherein the digital key provider is configured to provide the digital key at the output only when an enable-signal is provided to the enable-input; and a fuse unit comprising a first fuse and a second fuse, wherein the fuse unit is configured to provide the enable-signal to the enable-input when the first fuse is broken while the second fuse is intact.

Abstract: A film bulk acoustic resonator includes a substrate; an acoustic reflector portion formed on the substrate; and an acoustic resonator portion including a lower electrode, a piezoelectric film, and an upper electrode which are sequentially stacked on the acoustic reflector portion, An uppermost layer of the acoustic reflector portion which is in contact with the acoustic resonator portion has a root-mean-square roughness of approximately 1 nm or less.

Abstract: An impedance buffer has a single comparator with a first input and a second input. A first leg has a first pull-up array in series with a reference resistor. The first input of the single comparator is electrically coupled to a node between the first pull up array and the reference resistor. A second leg has a second pull-up array in series with a pull-down array. The second leg is coupled through a switch to the second input of the single comparator.

Abstract: A method is disclosed that includes propagating data via a first data path of a sequential circuit element in response to a clock signal received at a single clocked transistor of the sequential circuit element. The method also includes retaining information related to the data propagated via the first path at a retention circuit element of a second data path, where the first data path includes a first transistor that is responsive to an output of the single clocked transistor. The first transistor has a higher current flow capacity than a second transistor associated with the second data path.

Abstract: An electromagnetic composite metamaterial including an electromagnetic medium and a plurality of spaced electromechanical resonators disposed in or on the electromagnetic medium configured to control electromagnetic wave propagation properties in the electromagnetic composite metamaterial.

Abstract: In one embodiment, a programmable logic device includes a plurality of configuration cells that store configuration data, wherein the programmable logic device is adapted to provide soft error upset (SEU) protection for the configuration cells that are reprogrammable. The programmable logic device may further include or alternatively provide hard coding and/or hard encoding of the configuration cells.