Abstract: An integrated circuit includes multiple power domains. Supply current switch circuits (SCSCs) are distributed across each power domain. When a signal is present on a control node within a SCSC, the SCSC couples a local supply bus of the power domain to a global supply bus. An enable signal path extends through the SCSCs so that an enable signal can be propagated down a chain of SCSCs from control node to control node, thereby turning the SCSCs on one by one. When the domain is to be powered up, a control circuit asserts an enable signal that propagates down a first chain of SCSCs. After a programmable amount of time, the control circuit asserts a second enable signal that propagates down a second chain. By spreading the turning on of SCSCs over time, large currents that would otherwise be associated with coupling the local and global buses together are avoided.

Abstract: Various approaches for detection of an unwanted function implemented in an integrated circuit (IC) are described. A controller is implemented on the IC, and at a first time while the IC is operating according to a circuit design, the controller reads a first data set from a subset of memory cells. The subset of memory cells stores state information of the circuit design. The controller determines whether the first data set is different from a second data set. In response to the first data set being different from the second data set, the controller outputs a threat signal that indicates the presence of unauthorized logic in the circuit design.

Abstract: In a level conversion circuit, two P channel MOS transistors form a current mirror circuit. When an input signal rises from the “L” level to the “H” level, an N channel MOS transistor connected to a drain of one P channel MOS transistor is brought out of conduction to prevent a leak current from flowing through two P channel MOS transistors, which decreases a power consumption. In addition, when the input signal rises from the “L” level to the “H” level, a P channel MOS transistor connected to a drain of the other P channel MOS transistor is brought into conduction to fix a potential of a node of the drain of the other P channel MOS transistor to the “H” level, which prevents the potential of the node from becoming unstable.

Abstract: The present invention provides for a device to reduce the voltage swing for control signals. An input signal with a maximum potential of DVDD and minimum potential of AVSS is level shifted to a maximum potential of AVDD and a minimum potential of AVDD-DVDD. A series of control signals are generated from the level shifted input signal by standard logic cells. The shifting of the input signal reduces the voltage swing for the control signals. These control signals are then used to drive a device operating at a potential of AVDD.

Abstract: A rail-to-rail high speed subLVDS receiver demonstrates good jitter and duty cycle performance for high-speed signals at low power supply levels. A sample receiver includes a voltage shifter for shifting the voltage levels of a differential input signal so that a shifted differential input signal is produced. The shifted differential input signal can be applied to a first differential pair, and the differential input signal can be applied to a second differential pair. The outputs of the first and second differential pairs can be summed together to produce a differential output signal. The differential output signal can be output using an output block. A clamp circuit can be used to adjust the gain of the first differential pair responsive to a common mode voltage of the first and second differential input signals.

Abstract: An apparatus and method of reducing power consumption across a switch, such as an unprogrammed antifuse, is provided. The invention applies to antifuses, other switches such as transistor based switches, (e.g., FLASH, EEPROM and/or SRAM) and other devices exhibiting a leakage current, especially during a sleep or stand-by mode. During a sleep mode, such switches or other devices may be uncoupled from signals driving the switches, then terminals of each switch may be coupled to a common potential or allowed to float to a common potential thereby eliminating or reducing leakage currents through the switches.

Abstract: A semiconductor integrated circuit, able to repair a fault and normally operate as an overall circuit even when a fault occurs in a portion of the circuit, and able to reduce a change of signal delay along with the repair of the fault, including N (larger than 2) number of circuit modules which can replace each other's functions; circuit blocks each including R (larger than 1 but smaller than N) number of I/O units for outputting at least one signal to one circuit module, and receiving at least one signal generated in the one circuit module; and a circuit module selection unit configured to select R number of circuit modules from among the N number of circuit modules in response to a control signal, connect the selected R number of circuit modules and R number of I/O units of the circuit block in a 1:1 correspondence, and connect one circuit module selected from at least two circuit modules in response to the control signal to each of the R number of I/O units, and a method of producing the same.

Abstract: A terminal resistance adjusting method adjusts a terminating resistance within a semiconductor integrated circuit.

Abstract: A method to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated propagates a data signal cycle by cycle to a succeeding stage, comprising the steps of: deriving a local clock activation signal from an external clock activation signal, wherein said local clock activation signal changes its value every cycle the external clock activation signal indicates a propagation, propagating the data signal and the local clock activation signal synchronously cycle by cycle from a particular stage to a succeeding stage whenever a local clock activation signal at the particular stage by derivation from the clock activation signal or by propagation through the synchronous circuit changes its value between two successive cycles, in order to propagate the data signal and the local clock activating signal within the same clock domain through the clock gated synchronous circuit.

Abstract: An object of the present invention is to provide a technique of reducing the leakage current of a drive circuit for driving a circuit that must retain a potential (or information) when in its standby state. A semiconductor integrated circuit device of the present invention includes a drive circuit for driving a circuit block. This drive circuit is made up of a double gate transistor with gates having different gate oxide film thicknesses. When the circuit block is in its standby state, the gate of the double gate transistor having a thinner gate oxide film is turned off and that having a thicker gate oxide film is turned on. This arrangement allows a reduction in the leakage currents of both the circuit block and the drive circuit while allowing the drive circuit to deliver or cut off power to the circuit block.

Abstract: An apparatus, system, and method are described for synchronously resetting logic circuits. A synchronous reset signal is coupled to at least one asynchronous reset input for synchronously resetting sequential logic. In one embodiment, reset logic generates a signal coupled to the at least one asynchronous reset input of the sequential logic to synchronously reset the sequential logic.

Abstract: A design structure for an impedance matcher that automatically matches impedance between a driver and a receiver. The design structure for an impedance matcher includes a phase-locked loop (PLL) circuit that locks onto a data signal provided by the driver. The impedance matcher also includes tunable impedance matching circuitry responsive to one or more voltage-controlled oscillator control signals within the PLL circuit so as to generate an output signal that is impedance matched with the receiver.

Abstract: A waveguide in semiconductor integrated circuit is disclosed, the waveguide comprises a horizontal first metal plate, a horizontal second metal plate above the first metal plate, separated by an insulation material, and a plurality of metal vias positioned in two parallel lines, running vertically through the insulation material in contacts with both the first and second metal plates, wherein the first and second metal plates and the plurality of metal vias form a metal enclosure in a cross-sectional view that can serve as a waveguide.

Abstract: A semiconductor device, a test system and a method of testing an on die termination (ODT) circuit are disclosed. The semiconductor device includes an ODT circuit, a termination impedance control circuit and a boundary scan circuit. The termination impedance control circuit generates termination impedance control signals in response to a test mode command. The ODT circuit is coupled to the plurality of input/output pads and generates a plurality of termination impedances in response to the impedance control signals. The boundary scan circuit stores the termination impedances to output the stored termination impedances. Thus, the semiconductor device may test an ODT circuit accurately by using a smaller number of pins and may reduce a required time for testing the semiconductor device.

Abstract: Some embodiments provide a configurable integrated circuit with a tile. The tile has a first input multiplexer (IMUX), a second IMUX, and a look up table (LUT). The first IMUX is configured as a two-input multiplexer. The second IMUX is also configured as a two-input multiplexer. The LUT is also configured as a third two-input multiplexer. An output of the first IMUX is connected to the first input of the LUT, an output of the second IMUX is connected to the second input of the LUT. A third input of the LUT accepts a selection bit.

Abstract: A level shifter circuit and method of operating therefor. The level shifter circuit is coupled to receive a data signal via an input circuit, wherein the input circuit is in a first voltage domain. The level shifter circuit is also coupled to receive a clock signal from a second voltage domain. On a first portion of the clock cycle, true and complementary output nodes of the level shifter circuit (which are in the second voltage domain) are pulled to a first voltage by activation of respective pull transistors. On a second portion of the clock cycle, one of the true or complementary output nodes is pulled to a second voltage on a second voltage node by enabling the supply to the latch. Data is captured by the keeper, outputting true and complementary versions of the data signal in the second phase of the clock.

Abstract: Apparatus for configuring input/output signal levels of interfacing logic circuits operating at different voltage levels comprises: a logic circuit for operating at a first voltage level; a bank of input/output gates coupled to the logic circuit for interfacing input/output signals at a second voltage level, different from the first voltage level, to the logic circuit, the bank of gates including a port for setting the operational voltage level thereof; and a control circuit coupled to the port and governed by a control signal to configure the operational voltage level of the bank of gates to render the logic circuit and the interfacing input/output signals voltage level compatible.

Abstract: A pull-up circuit comprises an operational amplifier which forms part of a feedback circuit, acting to bring a pull-up circuit output equal to a reference voltage input. The pull-up circuit may form part of a USB transceiver for incorporation in a USB Device. When the supply voltage of the USB Device is sufficiently high, it is used to provide the required pull-up voltage, with the feedback circuit including the operational amplifier the USB Device is not high enough to provide the required pull-up voltage. In that case, the USB bus voltage is used to generate the reference voltage which is used as an input to the feedback circuit.

Abstract: A low-voltage differential signal driver for high-speed digital transmission includes a first converter operable to receive a signal in a first type and convert the signal into a second type, wherein a resistance of the first converter is variable. A second converter couples to the first converter, the second converter is operable to receive a signal in the second type and convert the signal into the first type, wherein a resistance of the second converter is variable. The driver is operable to scale the resistance of the first and second converters to provide a constant ratio between the resistance of the first and second converters.

Abstract: A low-voltage differential signal driver for high-speed digital transmission includes a first converter operable to receive a signal in a first type and convert the signal into a second type, and a cascode current mirror coupled to the first converter. The cascode current mirror provides an impedance level that increases a differential output voltage.