Abstract: An organic light-emitting display device and a method of fabricating the same are provided. The organic light-emitting display device includes a substrate having a plurality of trenches; a thin film transistor on the substrate; a light-emitting diode connected to the thin film transistor; an upper auxiliary electrode connected to one of an anode and a cathode of the light-emitting diode; and a lower auxiliary electrode in an auxiliary electrode trench among the plurality of trenches of the substrate and connected to the upper auxiliary electrode.

Abstract: A display device comprising a first substrate and a second substrate opposing one another, a thin film transistor and a color filter disposed on the first substrate, a planarization layer disposed on the thin film transistor and the color filter and a light blocking portion disposed on the planarization layer, the light blocking portion defining a pixel area, wherein the planarization layer comprises a first protrusion and a second protrusion, wherein the first protrusion is disposed in an area in which the light blocking portion is disposed, wherein the second protrusion is spaced apart from the first second protrusion, and wherein the light blocking portion comprises a first light blocking pattern disposed on the first protrusion, and the first light blocking pattern contacts the second substrate.

Abstract: An organic device, including semiconducting polymers processed from a solution cast on one or more dielectric layers on a substrate; and electrical contacts to the semiconducting polymers, wherein the substrate and the one or more dielectric layers are flexible and the semiconducting polymers are aligned. The one or more dielectric layers can increase mobility of the semiconducting polymers and/or alignment of the semiconducting polymers with one or more of the nanogrooves in the dielectric layers.

Abstract: To provide a display device in which variation in luminance among pixels is suppressed. The display device includes a transistor including first and second gates, first to third switches, first and second capacitors, a light-emitting element, and first and second wirings. The first gate is electrically connected to the first wiring through the first switch, a terminal of the transistor is electrically connected to the first gate through the third switch, and the second gate is electrically connected to the second wiring through the second switch. An anode of the light-emitting element is electrically connected to the terminal of the transistor. The first capacitor holds the capacitance between the first gate and the terminal of the transistor. The second capacitor holds the capacitance between the second gate and the terminal of the transistor.

Abstract: An anisotropic conductive film has a first connection layer and a second connection layer formed on surface of the first connection layer. The first connection layer is a photopolymerized resin layer, and the second connection layer is a thermo- or photo-cationically, anionically, or radically polymerizable resin layer. On the surface of first connection layer on the side of second connection layer, conductive particles for anisotropic conductive connection are arranged in a single layer. A region in which the curing ratio is lower than that of the surface of the first connection layer exists in a direction oblique to the thickness direction of the first connection layer. Alternatively, the curing ratio of a region relatively near another surface of the first connection layer among regions of the first connection layer in the vicinity of the conductive particles is lower than that of the surface of the first connection layer.

Abstract: Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.

Abstract: The present disclosure provides a packing assembly for a display panel. The packing assembly includes an adhesive layer, a first surface of the adhesive layer bonded onto a substrate; a plurality of deformable structures, and a plurality of packing assembly segments. The plurality of packing assembly segments are connected by the plurality of deformable structures, the plurality of packing assembly segments and the plurality of deformable structures being bonded onto a second surface of the adhesive layer.

Abstract: An apparatus comprising a chemical field effect transistor array in a circuit-supporting substrate is disclosed. The transistor array has disposed on its surface an array of sample-retaining regions capable of retaining a chemical or biological sample from a sample fluid. The transistor array has a pitch of 10 ?m or less and a sample-retaining region is positioned on at least one chemical field effect transistor which is configured to generate at least one output signal related to a characteristic of a chemical or biological sample in such sample-retaining region.

Abstract: An organic EL display device includes a substrate, a fin structure on the substrate, the fin structure standing upright in a thickness direction of the substrate, a first electrode formed on at least a part of a side surface of the fin structure, an organic film which is laminated so as to cover a surface of the first electrode on the side surface of the fin structure, a second electrode that is transparent and laminated so as to cover a surface of the organic film on the side surface and a top portion of the fin structure, a color filter layer that is formed on a path that light travels after being emitted from the light emitting layer and passing through the second electrode and formed at least above the organic film laminated on the side surface, and a light blocking layer configured to block light formed above the top portion of the fin structure.

Abstract: A device includes a semiconductor substrate, a plurality of micro-lenses disposed on the substrate, each micro-lens being configured to direct light radiation to a layer beneath the plurality of micro-lenses. The device further includes a transparent layer positioned between the plurality of micro-lenses and the substrate, the transparent layer comprising a structure that is configured to block light radiation that is traveling towards a region between adjacent micro-lenses, wherein the structure and the transparent material are coplanar at respective top surfaces and bottom surfaces thereof.

Abstract: Methods and apparatus relating to FET arrays including large FET arrays for monitoring chemical and/or biological reactions such as nucleic acid sequencing-by-synthesis reactions. Some methods provided herein relate to improving signal (and also signal to noise ratio) from released hydrogen ions during nucleic acid sequencing reactions.

Abstract: Methods and apparatus relating to FET arrays including large FET arrays for monitoring chemical and/or biological reactions such as nucleic acid sequencing-by-synthesis reactions. Some methods provided herein relate to improving signal (and also signal to noise ratio) from released hydrogen ions during nucleic acid sequencing reactions.

Abstract: A method for making a semiconductor device may include forming first and second spaced apart semiconductor active regions with an insulating region therebetween, forming at least one sacrificial gate line extending between the first and second spaced apart semiconductor active regions and over the insulating region, and forming sidewall spacers on opposing sides of the at least one sacrificial gate line. The method may further include removing portions of the at least one sacrificial gate line within the sidewall spacers and above the insulating region defining at least one gate line end recess, filling the at least one gate line end recess with a dielectric material, and forming respective replacement gates in place of portions of the at least one sacrificial gate line above the first and second spaced apart semiconductor active regions.

Abstract: An ESD cell includes an n+ buried layer (NBL) within a p-epi layer on a substrate. An outer deep trench isolation ring (outer DT ring) includes dielectric sidewalls having a deep n-type diffusion (DEEPN diffusion) ring (DEEPN ring) contacting the dielectric sidewall extending downward to the NBL. The DEEPN ring defines an enclosed p-epi region. A plurality of inner DT structures are within the enclosed p-epi region having dielectric sidewalls and DEEPN diffusions contacting the dielectric sidewalls extending downward from the topside surface to the NBL. The inner DT structures have a sufficiently small spacing with one another so that adjacent DEEPN diffusion regions overlap to form continuous wall of n-type material extending from a first side to a second side of the outer DT ring dividing the enclosed p-epi region into a first and second p-epi region. The first and second p-epi region are connected by the NBL.

Abstract: A silicon buffer layer selected from undoped silicon, p-doped silicon or a multilayered stack of, in any order, undoped silicon and p-doped silicon is provided between an n+ silicon layer and an oxide layer of an SOI substrate. The presence of the silicon buffer layer reduces electron injection into the oxide layer during device processing which requires an electric field.

Abstract: A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode.

Abstract: A semiconductor device includes a substrate having source and drain regions, and a channel region arranged between the source and drain regions. The device further includes a gate structure over the substrate and adjacent to the channel region. The gate structure includes a gate stack, a spacer on sidewalls of the gate stack, and a conductor over the gate stack. The device further includes a first contact feature over the substrate and electrically connecting to at least one of the source and drain regions. A top surface of the first contact feature is lower than a top surface of the gate structure. The device further includes a first dielectric layer over the first contact feature. A top surface of the first dielectric layer is below or substantially co-planar with the top surface of the gate structure. The conductor at most partially overlaps in plan view with the first dielectric layer.

Abstract: Among other things, one or more image sensors and techniques for forming image sensors are provided. An image sensor comprises a photodiode array configured to detect light. The image sensor comprises an oxide grid comprising a first oxide grid portion and a second oxide grid portion. A metal grid is formed between the first oxide grid portion and the second oxide grid portion. The oxide grid and the metal grid define a filler grid. The filler grid comprises a filler grid portion, such as a color filter, that allows light to propagate through the filler grid portion to an underlying photodiode. The oxide grid and the metal grid confine or channel the light within the filler grid portion. The oxide grid and the metal grid are formed such that the filler grid provides a relatively shorter propagation path for the light, which improves light detection performance of the image sensor.

Abstract: An alternating stack of insulating layers and sacrificial material layers are formed over a substrate. Memory stack structures are formed through the alternating stack. A backside trench is formed and the sacrificial material layers are replaced with electrically conductive layers. After formation of an insulating spacer in the trench, an epitaxial pedestal structure is grown from a semiconductor portion underlying the backside trench. A source region is formed by introducing dopants into the epitaxial pedestal structure and an underlying semiconductor portion during and/or after epitaxial growth. Alternatively, the backside trench can be formed concurrently with formation of memory openings. An epitaxial pedestal structure can be formed concurrently with formation of epitaxial channel portions at the bottom of each memory opening.

Abstract: An organic light-emitting device includes a substrate, an anode on the substrate, a hole transport region on the anode, an emission layer on the hole transport region, an electron transport region on the emission layer, and a cathode on the electron transport region, wherein the electron transport region includes an electron injection layer including a first material including at least one of a halide of an alkali metal, and a second material including at least one of a lanthanide metal and a alkaline earth metal, and wherein the cathode contacts the electron injection layer and includes a first metal including at least one of silver, gold, platinum, copper, manganese, titanium, cobalt, nickel, and tungsten, and a second metal including at least one of a lanthanide metal and an alkaline earth metal, wherein an amount of the first metal is equal to or greater than that of the second metal.