Patents Examined by Matthew Gordon
  • Patent number: 9780177
    Abstract: A thin film transistor array panel includes a gate line elongated in an extension direction and including a gate and dummy gate electrode extended therefrom; and a source electrode, and a single drain member including a drain electrode at a first end thereof and a dummy drain electrode at an opposing second end thereof. The drain electrode faces the source electrode with respect to the gate electrode, and the dummy drain electrode overlaps the dummy gate electrode. The drain and dummy drain electrode respectively include a plurality of first and second regions each having a predetermined width in the extension direction. A second region includes an edge which forms an angle from about 0 degrees to about 90 degrees with the extension direction, and a planar area of at least one of the plurality of second regions is different from that of remaining second regions.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: October 3, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jung Hwan Hwang, Bon-Yong Koo, Soo Jin Park, Jong-Moon Park, Yong Hee Lee, Jong-Hyuk Lee, Duc-Han Cho
  • Patent number: 9774008
    Abstract: An organic light-emitting diode (OLED) display device includes a substrate; a transistor device disposed on the substrate; a first electrode electrically connected to the transistor device; an organic light-emitting layer disposed on the first electrode; and a second electrode disposed on the organic light-emitting layer. The OLED display device further includes a transflective layer contacting a lower surface of the first electrode and having a relatively higher refractive index than the first electrode.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: September 26, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dong Min Lee, Hyun Eok Shin, Chan Woo Yang, Su Kyoung Yang
  • Patent number: 9754965
    Abstract: In one aspect, a method of forming a CMOS device includes forming nanowires suspended over a BOX, wherein a first/second one or more of the nanowires are suspended at a first/second suspension height over the BOX, and wherein the first suspension height is greater than the second suspension height; depositing a conformal gate dielectric on the BOX and around the nanowires wherein the conformal gate dielectric deposited on the BOX is i) in a non-contact position with the conformal gate dielectric deposited around the first one or more of the nanowires, and ii) is in direct physical contact with the conformal gate dielectric deposited around the second one or more of the nanowires such that the BOX serves as an oxygen source during growth of a conformal oxide layer at the interface between the conformal gate dielectric and the second one or more of the nanowires.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: September 5, 2017
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 9755001
    Abstract: A light-emitting device includes a first light-emitting element emitting blue light, a second light-emitting element emitting green light, and a third light-emitting element emitting red light. A first reflective electrode and a first transparent conductive film, a second reflective electrode and a second transparent conductive film, and a third reflective electrode and a third transparent conductive film are stacked in the first to third light-emitting elements, respectively. A first light-emitting layer, a charge-generation layer, a second light-emitting layer, and an electrode are stacked in this order over each of the first transparent conductive film, the second transparent conductive film, and the third transparent conductive film. The electrode has functions of transmitting and reflecting light. The first to third reflective electrodes contain silver. The first transparent conductive film is thicker than the third transparent conductive film.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: September 5, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Seo, Nobuharu Ohsawa, Toshiki Sasaki
  • Patent number: 9748292
    Abstract: A solid-state image sensing element including a transistor with stable electrical characteristics (e.g., significantly low off-state current) is provided. Two different element layers (an element layer including an oxide semiconductor layer and an element layer including a photodiode) are stacked over a semiconductor substrate provided with a driver circuit such as an amplifier circuit, so that the area occupied by a photodiode is secured. A transistor including an oxide semiconductor layer in a channel formation region is used as a transistor electrically connected to the photodiode, which leads to lower power consumption of a semiconductor device.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: August 29, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9728634
    Abstract: Methods of fabricating vertical devices are described, along with apparatuses and systems that include them. In one such method, a vertical device is formed at least partially in a void in a first dielectric material and a second dielectric material. Additional embodiments are also described.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: August 8, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Marcello Mariani, Carlo Pozzi
  • Patent number: 9728481
    Abstract: An IC system includes low-power chips, e.g., memory chips, located proximate one or more higher power chips, e.g., logic chips, without suffering the effects of overheating. The IC system may include a high-power chip disposed on a packaging substrate and a low-power chip embedded in the packaging substrate to form a stack. Because portions of the packaging substrate thermally insulate the low-power chip from the high-power chip, the low-power chip can be embedded in the IC system in close proximity to the high-power chip without being over heated by the high-power chip. Such close proximity between the low-power chip and the high-power chip advantageously shortens the path length of interconnects therebetween, which improves device performance and reduces interconnect parasitics in the IC system.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: August 8, 2017
    Assignee: NVIDIA Corporation
    Inventors: Abraham F. Yee, Joe Greco, Jun Zhai, Joseph Minacapelli, John Y. Chen
  • Patent number: 9721509
    Abstract: An active matrix organic light emitting diode (OLED) display device includes an array of pixels, each pixel including an OLED, a driving transistor (DT) coupled to drive current through the OLED, a storage capacitor, and a scanning transistor (ST) coupled to control charge on the storage capacitor corresponding to a data voltage for said pixel. The display device also includes a timing controller configured to control the ST of each pixel to update the charge stored on the storage capacitor of each pixel at a frame rate including at least one frequency within a range of 1-10 Hertz (Hz).
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: August 1, 2017
    Assignee: LG Display Co., Ltd.
    Inventors: Junghyeon Kim, Hyungjin Bang
  • Patent number: 9716247
    Abstract: Various embodiments may relate to an optoelectronic component, including a carrier, a planar, electrically active region on or above the carrier; an adhesion layer on or above the electrically active region, wherein the adhesion layer at least partly surrounds the electrically active region, a cover on or above the adhesion layer, wherein a part of the adhesion layer is exposed, and an encapsulation on or above the exposed adhesion layer, wherein the encapsulation is formed from an inorganic substance or substance mixture. Further various embodiments may relate to a method for producing an optoelectronic component.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: July 25, 2017
    Assignee: OSRAM OLED GmbH
    Inventors: Simon Schicktanz, Philipp Schwamb, Evelyn Trummer-Sailer
  • Patent number: 9711562
    Abstract: A method includes forming a plurality of pixels formed on a front surface of a semiconductor substrate, forming an array of color filters over the plurality of pixels, each color filter being adapted for allowing a wavelength of light radiation to reach at least one of the plurality of pixels, forming a plurality of micro-lenses over the array of color filters, and forming a second layer between the pixels and the color filters. The second layer further includes a structure adapted for blocking light radiation that is traveling towards a region between adjacent micro-lens, further wherein the plurality of micro-lenses are in contact with the array of color filters, and wherein the structure and the transparent material are coplanar at respective top surfaces thereof, and further wherein the structure directly contacts a bottom surface of at least one of the color filters.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: July 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Min Lin, Ching-Chun Wang, Dun-Nian Yaung, Chun-Ming Su, Tzu-Hsuan Hsu
  • Patent number: 9711561
    Abstract: A solid-state imaging device including is provided. The solid-state imaging device includes: pixels arrayed; a photoelectric conversion element in each of the pixels; a read transistor for reading electric charges photoelectrically-converted in the photoelectric conversion elements to a floating diffusion portion; a shallow trench element isolation region bordering the floating diffusion portion; and an impurity diffusion isolation region for other element isolation regions than the shallow trench element isolation region.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: July 18, 2017
    Assignee: Sony Corporation
    Inventors: Kazuichiro Itonaga, Yu Oya
  • Patent number: 9711691
    Abstract: A light emitting device has a base body equipped with a base material and a pair of connection terminals disposed from a first main face to a second main face that is on the opposite side from the first main face; a plurality of light emitting elements connected to the connection terminals on the first main face; and a light reflecting member that covers the side faces of the light emitting elements, the base material having a protruding component on the second main face, the protruding component being one of a heat releasing terminal, a reinforcement terminal, and an insulating film, and the connection terminals being disposed on the first main face from the second main face on both sides of the protruding component, and being partly exposed from the light reflecting member on both sides of the first main face.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: July 18, 2017
    Assignee: NICHIA CORPORATION
    Inventors: Hiroto Tamaki, Takuya Nakabayashi
  • Patent number: 9698230
    Abstract: A semiconductor device includes a source and drain on a substrate; a first and second gate on the source, and the second gate and a third gate on the drain; a source contact over the source and between the first and second gates, the source contact including first and second portions, the first portion in contact with the source and extending between the first and second gates, and the second portion contacting the first portion and extending over the first and second gates; and a drain contact formed over the drain and between the second and third gates, the drain contact including first and second portions, the first portion contacting the drain, extending between second and third gates, and recessed with respect to the first portion of the source contact, and the second portion in contact with the first portion and extending between and over the second and third gates.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: July 4, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Kangguo Cheng, Xin Miao, Ruilong Xie, Tenko Yamashita
  • Patent number: 9691836
    Abstract: A pixel unit is used in an array substrate of a display device. In one embodiment, it comprises a gate line, a source-drain line and a thin-film transistor; and the gate line is in an overlapped structure comprising a first MoW layer, a Cu layer and a second MoW layer overlapped successively; and a gate of the thin-film transistor is formed of the first MoW layer. In another embodiment, the source-drain line is in a same overlapped structure; and a source and a drain of the thin-film transistor are formed of the first MoW layer. The first embodiment is achieved by means of a halftone process while the second embodiment is achieved by means of a lift off process. Diffusion of Cu in the gate layer or in the source-drain layer towards the oxide active layer is prevented.
    Type: Grant
    Filed: December 25, 2014
    Date of Patent: June 27, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Chunsheng Jiang, Jingfei Fang, Baojiang Zhang
  • Patent number: 9691828
    Abstract: The invention provides a display apparatus and a method for manufacturing the same, relates to the field of display technology, and solves the problem of low display luminance due to the existing display apparatus being affected by other film layers. A display apparatus comprises a light emitting unit and further comprises several layers of thin film located in the light emission path of the light emitting unit, and at least one of the several layers of thin film has nanoparticles.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: June 27, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhiqiang Jiao, Shibo Jiao, Chengyuan Luo
  • Patent number: 9691897
    Abstract: A three-dimensional transistor includes a semiconductor substrate, a fin coupled to the substrate, the fin including an active region across a top portion thereof, the active region including a source, a drain and a channel region therebetween. The transistor further includes a gate situated above the channel region, and a gate contact situated in the active region, no portion thereof being electrically coupled to the source or drain. The transistor is achieved by removing a portion of the source/drain contact situated beneath the gate contact during fabrication.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: June 27, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Andre Labonte, Andreas Knorr
  • Patent number: 9691867
    Abstract: The semiconductor device structures and methods for forming the same are provided. The semiconductor device structure includes a metal gate over a substrate. A first spacer is formed over sidewalls of the metal gate and having a first height. A second spacer is formed over the sidewalls of the metal gate and having a second height. The first height is higher than the second height. The first spacer is farther from the sidewalls of the metal gate than the second spacer. In addition, the semiconductor device structure includes a dielectric layer formed over the substrate to surround the first spacer and the metal gate.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: June 27, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Liang Liao, Chih-Hsiao Chen, Yi-Lii Huang, Yao-Yu Li
  • Patent number: 9692018
    Abstract: An organic light emitting display apparatus includes: a substrate divided into an emission area and a non-emission area; a pixel electrode disposed in the emission area; an intermediate layer disposed on the pixel electrode, including an organic emission layer; a counter electrode covering the intermediate layer; an external light reflection layer disposed on the counter electrode, the external light reflection layer being configured to reflect a portion of incident visible rays; and absorb and transmit another portion of the incident visible rays; a phase control layer disposed between the counter electrode and the external light reflection layer, being configured to control a phase of a light reflected by the counter electrode to destructive interfere with light reflected by the external light reflection layer; a thin-film encapsulating layer disposed on the external light reflection layer; and a black matrix disposed on the thin-film encapsulating layer in the non-emission area.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: June 27, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sanghwan Cho, Chungsock Choi, Seunghun Kim, Cheol Jang
  • Patent number: 9692017
    Abstract: An organic light emitting diode can include a first electrode and a second electrode; an organic light emitting layer between the first electrode and the second electrode; and a auxiliary light emitting layer between the first electrode and the organic light emitting layer or between the organic light emitting layer and the second electrode, wherein a difference between a main peak wavelength of light emitted from the organic light emitting layer itself and a main peak wavelength of light out-coupling between the first and second electrodes is within a predetermined range.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: June 27, 2017
    Assignee: LG Display Co., Ltd.
    Inventors: Ho-Sung Kim, Mi-Na Kim
  • Patent number: 9685395
    Abstract: A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: June 20, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Kong-Beng Thei, Chih-Tsung Yao, Heng-Kai Liu, Ming-Jer Chiu, Chien-Wen Chen