Patents Examined by Matthew Gordon
  • Chip package including recess in side edge
    Patent number: 9620431
    Abstract: A chip package including a semiconductor substrate is provided. A recess is in the semiconductor substrate, wherein the semiconductor substrate has at least one spacer protruding from the bottom of the recess. A conducting layer is disposed on the semiconductor substrate and extends into the recess. A method for forming the chip package is also provided.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: April 11, 2017
    Assignee: XINTEC INC.
    Inventors: Chia-Ming Cheng, Tsang-Yu Liu, Chi-Chang Liao, Yu-Lung Huang
  • Methods and apparatus for measuring analytes
    Patent number: 9618475
    Abstract: Methods and apparatus relating to FET arrays including large FET arrays for monitoring chemical and/or biological reactions such as nucleic acid sequencing-by-synthesis reactions. Some methods provided herein relate to improving signal (and also signal to noise ratio) from released hydrogen ions during nucleic acid sequencing reactions.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: April 11, 2017
    Assignee: Life Technologies Corporation
    Inventors: Jonathan Rothberg, Todd Rearick
  • Nano-ribbon channel transistor with back-bias control
    Patent number: 9614037
    Abstract: Embodiments of the invention include a method for fabricating a nano-ribbon transistor device and the resulting structure. A nano-ribbon transistor device including a substrate, a nano-ribbon channel, a core region in the center of the nano-ribbon channel, a gate formed around the nano-ribbon channel, a spacer formed on each sidewall of the gate, and a source and drain region epitaxially formed adjacent to each spacer is provided. The core region in the center of the nano-ribbon channel is selectively etched. A dielectric material is deposited on the exposed portions of the nano-ribbon channel. A back-bias control region is formed on the dielectric material within the core of the nano-ribbon channel and on the substrate adjacent to the nano-ribbon transistor device. A metal contact is formed in the back-bias control region.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: April 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Display panel including multilayer diffusion barrier
    Patent number: 9608238
    Abstract: Disclosed is a display panel including: a flexible substrate; a buffer layer disposed on the flexible substrate; a pixel disposed on the buffer layer and comprising a thin film transistor and an image device connected to the thin film transistor; a barrier layer disposed on the flexible substrate to protect the pixel from a substance from the flexible substrate; and a diffusion prevention layer disposed between the barrier layer and the buffer layer and configured to prevent hydrogen generated from the barrier layer from being diffused into the thin film transistor.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: March 28, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jintaek Kim, Jong Yun Kim, Cheolho Yu
  • Memory circuit including oxide semiconductor devices
    Patent number: 9608005
    Abstract: To provide a semiconductor device with excellent charge retention characteristics, an OS transistor is used as a transistor whose gate is connected to a node for retaining charge. Charge is stored in a first capacitor, and data at the node for retaining charge is read based on whether the stored charge is transferred to a second capacitor. Since a Si transistor, in which leakage current through a gate insulating film occurs, is not used as a transistor connected to the node for retaining charge, charge retention characteristics of the node are improved. In addition, the semiconductor device operates in data reading without requiring transistor performance equivalent to that of a Si transistor.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: March 28, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Masami Endo
  • Fin trimming in a double sit process
    Patent number: 9601345
    Abstract: A semiconductor structure and the method of forming that semiconductor structure. The method includes formation of a plurality of fins from a layer of semiconductor material. At least one fin of the plurality of fins is at least fifty percent wider than each of a group of fins included in the plurality of fins. The method also includes selectively removing the one fin such that only the group of fins remain.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: March 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Matthew E. Colburn, Bruce B. Doris, Ali Khakifirooz
  • Chip package including recess in side edge
    Patent number: 9601460
    Abstract: A chip package including a semiconductor substrate is provided. A recess is in the semiconductor substrate and adjoins a side edge of the semiconductor substrate, wherein the semiconductor substrate has at least one spacer protruding from the bottom of the recess. A conducting layer is disposed on the semiconductor substrate and extends into the recess.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: March 21, 2017
    Assignee: XINTEC INC.
    Inventors: Yen-Shih Ho, Tsang-Yu Liu, Chia-Sheng Lin, Chia-Ming Cheng, Shu-Ming Chang, Tzu-Wen Tseng
  • Diode structure compatible with FinFET process
    Patent number: 9601627
    Abstract: An embodiment integrated circuit (e.g., diode) and method of making the same. The embodiment integrated circuit includes a well having a first doping type formed over a substrate having the first doping type, the well including a fin, a source formed over the well on a first side of the fin, the source having a second doping type, a drain formed over the well on a second side of the fin, the drain having the first doping type, and a gate oxide formed over the fin, the gate oxide laterally spaced apart from the source by a back off region of the fin. The integrated circuit is compatible with a FinFET fabrication process.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Che Tsai, Yi-Feng Chang, Jam-Wem Lee
  • Semiconductor devices and arrangements including dummy gates for electrostatic discharge protection
    Patent number: 9595516
    Abstract: A semiconductor device and device arrangement including a plurality of semiconductor regions of different conductivity types and a plurality of gates which form electrically conducting paths between the semiconductor regions. The semiconductor device and device arrangement may be configured to protect against electrostatic discharge.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: March 14, 2017
    Assignee: INTEL IP CORPORATION
    Inventors: Mayank Shrivastava, Christian Russ
  • Device comprising a ductile layer and method of making the same
    Patent number: 9576867
    Abstract: Device comprising a ductile layer, a method for making a component comprising a ductile layer and a method for testing a component are disclosed. An embodiment includes an electronic device including a first conductive layer, a ductile layer and a brittle layer between the first conductive layer and the ductile layer.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: February 21, 2017
    Assignee: Infineon Technologies AG
    Inventors: Georg Meyer-Berg, Reinhard Pufall
  • Semiconductor device including spiral shape inductor and horseshoe shape inductor
    Patent number: 9577698
    Abstract: A semiconductor device includes a plurality of first inductors having a spiral shape and provided in a modulator of a transmitting side, and a plurality of second inductors having a horseshoe shape and provided in an oscillator of a receiving side, the plurality of second inductors being arranged such that an opening of plurality of second inductors is disposed opposite to the plurality of first inductors. The semiconductor device performs a transmission process and a reception process using a radio wave.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: February 21, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takao Kihara
  • Organic light-emitting display apparatus and method of manufacturing the same including RGB insulating layer configuration
    Patent number: 9570710
    Abstract: An organic light-emitting display apparatus, including a substrate; a first reflective layer, a second reflective layer, and a third reflective layer that are separately disposed on the substrate; a first insulating layer on the first reflective layer, but not on the second reflective layer and the third reflective layer; a second insulating layer on the first insulating layer and the second reflective layer, but not on the third reflective layer; and a first pixel electrode for red emission on the second insulating layer and corresponding to the first reflective layer, a second pixel electrode for green emission on the second insulating layer and corresponding to the second reflective layer, and a third pixel electrode for blue emission on the third reflective layer.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: February 14, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jaehwan Oh, Jaebeom Choi, Sehun Park, Yongduck Son, Jiyoun Lee, Youngjin Chang
  • Fully-printed carbon nanotube thin film transistor circuits for organic light emitting diode
    Patent number: 9564481
    Abstract: The subject technology relates to a method including steps for disposing a first electrically conductive material on a substrate to form a first layer of electrodes on the substrate, wherein the first layer includes a source electrode and a drain electrode, and printing a film including carbon nanotubes between the source electrode and the drain electrode, thereby defining at least a first interface between the carbon nanotube film and the source electrode and a second interface between the carbon nanotube film and drain electrode. In certain aspects, the method can further include steps for disposing a second electrically conductive material over the first interface between the carbon nanotube film and the source electrode and the second interface between the carbon nanotube film and the drain electrode. In certain aspects, a transistor device is also provided.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: February 7, 2017
    Assignees: ANEEVE LLC, The Regents of the University of California, The University of Southern California
    Inventors: Chongwu Zhou, Kosmas Galatsis, Pochiang Chen, Yue Fu
  • Dual channel finFET with relaxed pFET region
    Patent number: 9559018
    Abstract: Fabricating a semiconductor device includes providing a strained semiconductor material (SSM) layer disposed on a dielectric layer, forming a first plurality of fins on the SSOI structure, at least one fin of the first plurality of fins is in a nFET region and at least one fin is in a pFET region, etching portions of the dielectric layer under portions of the SSM layer of the at least one fin in the pFET region, filling areas cleared by the etching, forming a second plurality of fins from the at least one fin in the nFET region such that each fin comprises a portion of the SSM layer disposed on the dielectric layer, and forming a third plurality of fins from the at least one fin in the pFET region such that each fin comprises a portion of the SSM layer disposed on a flowable oxide.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: January 31, 2017
    Assignees: International Business Machines Corporation, Globalfoundries, Inc., STMicroelectronics, Inc.
    Inventors: Xiuyu Cai, Qing Liu, Ruilong Xie, Chun-Chen Yeh
  • Method of manufacturing nitride semiconductor template
    Patent number: 9558938
    Abstract: A method of manufacturing a nitride semiconductor template that includes a base substrate of a sapphire substrate and a nitride semiconductor layer represented by a general formula AlxGa1-xN (0.3?x?1) includes: contacting the base substrate with a water vapor atmosphere, nitriding a surface of the base substrate by contacting the base substrate with a nitrogen raw material to form a nitrided area on the surface of the base substrate, and growing a nitride semiconductor layer on the nitrided area.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: January 31, 2017
    Assignee: NICHIA CORPORATION
    Inventors: Hideyuki Gono, Yosuke Shimada
  • Dynamic strain sensor and method
    Patent number: 9557229
    Abstract: A dynamic strain sensor includes a strain sensitive transistor and a light emitting diode coupled to the strain sensitive transistor. The dynamic strain sensor can include a piezoelectric layer incorporated into the structure of the strain sensitive transistor. The dynamic strain sensor can sense dynamic strain and can measure and monitor the dynamic strain wirelessly.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: January 31, 2017
    Assignee: Honeywell Romania s.r.l.
    Inventors: Viorel Georgel Dumitru, Stefan Dan Costea, Ion Georgescu, Mihai Brezeanu
  • Solid-state imaging device and camera including discrete trench isolation structure
    Patent number: 9543350
    Abstract: A solid-state imaging device including is provided. The solid-state imaging device includes: pixels arrayed; a photoelectric conversion element in each of the pixels; a read transistor for reading electric charges photoelectrically-converted in the photoelectric conversion elements to a floating diffusion portion; a shallow trench element isolation region bordering the floating diffusion portion; and an impurity diffusion isolation region for other element isolation regions than the shallow trench element isolation region.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: January 10, 2017
    Assignee: Sony Corporation
    Inventors: Kazuichiro Itonaga, Yu Oya
  • Techniques for dual dielectric thickness for a nanowire CMOS technology using oxygen growth
    Patent number: 9536794
    Abstract: In one aspect, a method of forming a CMOS device includes forming nanowires suspended over a BOX, wherein a first/second one or more of the nanowires are suspended at a first/second suspension height over the BOX, and wherein the first suspension height is greater than the second suspension height; depositing a conformal gate dielectric on the BOX and around the nanowires wherein the conformal gate dielectric deposited on the BOX is i) in a non-contact position with the conformal gate dielectric deposited around the first one or more of the nanowires, and ii) is in direct physical contact with the conformal gate dielectric deposited around the second one or more of the nanowires such that the BOX serves as an oxygen source during growth of a conformal oxide layer at the interface between the conformal gate dielectric and the second one or more of the nanowires.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: January 3, 2017
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Jeffrey W. Sleight
  • Display device including tapered substrate
    Patent number: 9537013
    Abstract: A display device is provided including a first substrate comprising a resin material provided with a plurality region provided with a plurality of pixels including a display device, and a second substrate provided facing the first substrate and installed with the pixel region, wherein an outer periphery side surface of the first substrate having a taper shape and including a barrier layer covering an upper layer, lower layer and the outer periphery side surface of the first substrate.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: January 3, 2017
    Assignee: Japan Display Inc.
    Inventors: Takuma Nishinohara, Toshihiko Itoga, Norio Oku, Yasukazu Kimura, Jun Fujiyoshi
  • Non-volatile memory device
    Patent number: 9536894
    Abstract: According to an embodiment, a non-volatile memory device includes first electrodes arranged in a first direction, a second electrode disposed on a side of the first electrodes in the first direction, a semiconductor layer extending in the first direction through the first electrodes and the second electrode, and a memory film provided between the semiconductor layer and each of the first electrodes. The semiconductor layer includes crystal grains and has a first portion and a second portion, the first portion being adjacent to the first electrodes, and the second portion being adjacent to at least a part of the second electrode, wherein the first portion includes a larger crystal grain than a crystal grain in the second portion.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: January 3, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hikari Tajima, Masaki Kondo, Tsukasa Nakai, Takashi Izumida, Hiroki Tokuhira