Abstract: The escape surface of a light emitting element includes features that include sloped surfaces that have angles of inclination that are based on the direction of peak light output from the light emitting element. If the light output exhibits a number of lobes at different directions, the sloped surfaces may have a corresponding number of different angles of inclination. To minimize the re-injection of light into adjacent features, adjacent features may be positioned to avoid having surfaces that directly face each other. The features may be shaped or positioned to provide a pseudo-random distribution of inclined surfaces across the escape surface, and multiple roughening processes may be used.

Abstract: Embodiments of the present invention are directed to techniques for forming a robust low-k bottom spacer for a vertical field effect transistor (VFET) using a spacer first, shallow trench isolation last process integration. In a non-limiting embodiment of the invention, a semiconductor fin is formed over a substrate. A first dielectric liner is formed on a sidewall of the semiconductor fin. A bottom spacer is formed over the substrate and on a sidewall of the first dielectric liner. The first dielectric liner is positioned between the semiconductor fin and the bottom spacer. Portions of the bottom spacer are removed to define a shallow trench isolation region.

Abstract: A modular quantum computer architecture is developed with a hierarchy of interactions that can scale to very large numbers of qubits. Local entangling quantum gates between qubit memories within a single modular register are accomplished using natural interactions between the qubits, and entanglement between separate modular registers is completed via a probabilistic photonic interface between qubits in different registers, even over large distances. This architecture is suitable for the implementation of complex quantum circuits utilizing the flexible connectivity provided by a reconfigurable photonic interconnect network. The subject architecture is made fault-tolerant which is a prerequisite for scalability.

Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a capacitor. The capacitor may include a first electrode, a second electrode, and a paraelectric layer between the first electrode and the second electrode. A first interface with a first work function exists between the paraelectric layer and the first electrode. A second interface with a second work function exists between the paraelectric layer and the second electrode. The paraelectric layer may include a ferroelectric material or an anti-ferroelectric material. A built-in electric field associated with the first work function and the second work function may exist between the first electrode and the second electrode. The built-in electric field may be at a voltage value where the capacitor may operate at a center of a memory window of a polarization-voltage hysteresis loop of the capacitor. Other embodiments may be described and/or claimed.

Abstract: A mid-infrared detector that uses a heavily doped material (e.g., indium arsenide) as a backplane to the detector structure to improve detector performance and fabrication cost. The infrared detector includes a substrate and a backplane of heavily doped material consisting of two or more of the following materials: indium, gallium, arsenic and antimony. The backplane resides directly on the substrate. The infrared detector further includes a photodetector (e.g., type-I or type-II strained layer superlattice (SLS) nBn photodetector, type-I or type-II SLS pn junction photodetector, a quantum-dot infrared photodetector, a quantum well infrared photodetector, a homogeneous material pn junction photodetector) residing directly on the backplane. Additionally, the infrared detector may include a metal structure residing directly on the photodetector. In this manner, the absorption of electromagnetic energy in the photodetector is enhanced.

Abstract: A quantum controller comprises a quantum control pulse generation circuit and digital signal management circuit. The quantum control pulse generation circuit is operable to generate a quantum control pulse which can be processed by any of a plurality of controlled circuits, and generate a first digital signal which can be routed to any of the plurality of controlled circuits. The digital signal management circuit is operable to detect, during runtime, to which one or more of the plurality of controlled circuits the first digital signal is to be routed, to manipulate the first digital signal based on the one or more of the plurality of controlled circuits to which the first digital signal is to be routed, where the manipulation results in one or more manipulated digital signals, and to route the one or more manipulated digital signals to one or more of the plurality of controlled circuits.

Abstract: A unit includes a wiring board having a first face having a mounting portion on which an electronic device is mounted, a second face opposite to the first face, and end faces continuous with the first face and the second face, a resin member provided to cover the end faces and to have protrusions protruding upward from the end faces to face each other across a space above the mounting portion, and an insulating film covering the second face, wherein at least a part of an edge of the insulating film is provided away from an end of the second face on the end face side.

Abstract: Lattice arrangements for quantum qubits are described. A lattice arrangement can comprise adjacent structures having vertices connected by edges. The qubits can be positioned on the vertices. A qubit in the lattice arrangement directly connects to not more than three other qubits, or connects to another qubit via a coupling qubit on an edge between two qubits on a vertex. The adjacent structures can comprise hexagons, dodecagons or octagons. A superconducting qubit lattice can comprise superconducting target qubits and superconducting control qubits. The superconducting qubit lattice can comprise adjacent structures having vertices connected by edges, with target qubits positioned on the vertices and control qubits positioned on the edges. Logic operations between adjacent superconducting target and control qubits can be implemented by driving the superconducting control qubit at or near the frequency of the superconducting target qubit.

Abstract: Techniques regarding encapsulating one or more superconducting devices of a quantum processor are provided. For example, one or more embodiments described herein can regard a method that can comprise depositing a metal fluoride layer onto a superconducting resonator and a silicon substrate that can be comprised within a quantum processor. The superconducting resonator can be positioned on the silicon substrate. Also, the metal fluoride layer can coat the superconducting resonator.

Abstract: A display apparatus includes a base substrate, an active pattern disposed on the base substrate, a gate insulation layer disposed on the active pattern, a gate electrode disposed on the gate insulation layer and overlapping the active pattern, a first insulation layer disposed on the gate electrode and having a total amount of hydrogen of about 5 atomic percent (at. %) to about 30 at. %, and a source electrode and a drain electrode which are disposed on the first insulation layer and are electrically connected to the active pattern.

Abstract: Techniques for simulating a quantum circuit based on fusion of at least a portion of a measure gate is provided. Data representing a quantum circuit comprising a quantum gate and a measure gate is received. The measure gate in the quantum circuit is divided into one or more virtual gates and at least one of the one or more virtual gates is fused with the quantum gate. The gate fusion combines the operations of the fused gates and cache blocking to more efficiently simulate the quantum circuit. In one embodiment, the simulation of the quantum circuit is executed locally on a computing device. Alternatively, the simulation of the quantum circuit is performed remotely over a network via an application program interface (“API”) and results of the simulation are reported via the API.

Abstract: A quantum computer task manager is provided. The quantum computer task manager executes on a quantum computing system that utilizes a plurality of qubits. The quantum computer task manager accesses first data associated with a first quantum service to determine a first subset of qubits used by the first quantum service. For at least one qubit of the first subset of qubits, the quantum computer task manager determines either a superposition status or an entanglement status of the at least one qubit, and communicates to a destination information that identifies the first quantum service, the at least one qubit, and either the superposition status of the at least one qubit or the entanglement status of the at least one qubit.

Abstract: This disclosure relates to fabrication of step edges to fabricate Josephson junctions. A method comprises forming a layer of resist over the surface. The layer of resist comprises openings to expose a selected area of the surface, thereby forming two walls in the layer of resist on a perimeter of the selected area. The resist and the substrate are exposed to an ion beam, thereby etching the resist and the exposed areas of the surface. While exposing the resist and the substrate to the ion beam, the substrate is gradually rotated about an axis normal to the surface to thereby form two step edges at the respective two walls. Further, superconducting material is deposited onto the substrate in a meandering shape to form a path that crosses the two step edges multiple times and to form a Josephson junction each time the path crosses the step edges.

Abstract: A light reception/emission element module comprises a substrate, a light emitting element disposed on the substrate, a first light receiving device disposed on the substrate apart from the light emitting element, and an upper wall located above the substrate. The upper wall comprises a facing surface facing the light emitting element and the first light receiving element. The light reception/emission element module of the disclosure further comprises a second light emitting element disposed on the substrate. The upper wall further comprises a first light passing portion located above the light emitting element, a second light passing portion located above the second light receiving element, and an intermediate portion located in a region between the first light passing portion and the second light passing portion. At least part of a lower surface of the intermediate portion comprises the facing surface.

Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.

Abstract: Embodiments of the disclosed technology concern a quantum circuit configured to implement a real time evolution unitary of a Hamiltonian in a quantum computing device, wherein a unit time evolution unitary operator is decomposed into overlapping smaller blocks of unitary operators. In some implementations, (a) the size of the overlap is proportional to the logarithm of a number of qubits in the simulated system, (b) the size of the overlap is proportional to the logarithm of a total simulated evolution time, and/or (c) the size of the overlap is proportional to a Lieb-Robinson velocity.

Abstract: This spin-orbit-torque magnetization rotating element includes a spin-orbit torque wiring extending in a first direction and a first ferromagnetic layer laminated on the spin-orbit torque wiring, wherein the spin-orbit torque wiring includes a compound represented by XYZ or X2YZ with respect to a stoichiometric composition.

Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures.

Abstract: Quantum circuits and methods load N=2n classical bits into an entangled quantum output state using a gate depth of order O(n). Loading is accomplished by dividing the 2n input bits into data words and entangling these data words using ancilla qubits. The output of the circuit consists of one data word and one or several index qubits, drawn from the ancilla, to select between the input data words. Entanglement of the data words is performed in a single time slice (i.e. with a gate depth of 1), while the number of sequential gates needed to produce the appropriate pre-entanglement quantum state in the ancilla, and to disentangle the non-output ancilla, has the desired order O(n). Also disclosed is a circuit for disentangling qubits used to store non-output data words during processing.

Abstract: According to an embodiment of the present invention, a quantum mechanical device includes a monolithic crystalline structure. The monolithic crystalline structure includes a first region doped to provide a first superconducting region, and a second region doped to provide a second superconducting region, the second superconducting region being separated from the first superconducting region by an undoped crystalline region. The first and second superconducting regions and the undoped crystalline region form a Josephson junction.