Abstract: A manufacturing method of a memory device includes the following steps. Memory units are formed on a substrate. Each of the memory units includes a first electrode, a second electrode, and a memory material layer. The second electrode is disposed above the first electrode in a vertical direction. The memory material layer is disposed between the first electrode and the second electrode in the vertical direction. A conformal spacer layer is formed on the memory units. A non-conformal spacer layer is formed on the conformal spacer layer. A first opening is formed penetrating through a sidewall portion of the non-conformal spacer layer and a sidewall portion of the conformal spacer layer in the vertical direction.

Abstract: In one aspect, a method includes forming an electrical path between p-type mercury cadmium telluride and a metal layer. The forming of the electrical path includes depositing a layer of polycrystalline p-type silicon directly on to the p-type mercury cadmium telluride and forming the metal layer on the layer of polycrystalline p-type silicon. In another aspect, an apparatus includes an electrical path. The electrical path includes a p-type mercury cadmium telluride layer, a polycrystalline p-type silicon layer in direct contact with the p-type mercury cadmium telluride layer, a metal silicide in direct contact with the polycrystalline p-type silicon layer, and an electrically conductive metal on the metal silicide. In operation, holes, indicative of electrical current on the electrical path, flow from the p-type mercury cadmium telluride layer to the electrically conductive metal.

Abstract: A photodetector designing method includes, according to various requirements required by an application equipped with a photodetector including a photoelectric conversion layer having a superlattice structure mostly composed of amorphous selenium, a step of determining a form of the photodetector; a step of determining a type of a substrate suitable for a wavelength to be detected by the photoelectric conversion layer among the requirements, a step of calculating a multiplication factor M representing an amplification gain generated in a process of tunneling in the superlattice structure, and a step of determining, as a layer thickness of the photoelectric conversion layer, a thickness obtained by multiplying a thickness per one layer of the superlattice structure by the number of layers NSL of the superlattice structure on the assumption that the multiplication factor M is approximate to the number of layers NSL.

Abstract: A modular quantum computer architecture is developed with a hierarchy of interactions that can scale to very large numbers of qubits. Local entangling quantum gates between qubit memories within a single modular register are accomplished using natural interactions between the qubits, and entanglement between separate modular registers is completed via a probabilistic photonic interface between qubits in different registers, even over large distances. This architecture is suitable for the implementation of complex quantum circuits utilizing the flexible connectivity provided by a reconfigurable photonic interconnect network. The subject architecture is made fault-tolerant which is a prerequisite for scalability.

Abstract: A semiconductor structure can comprise a plurality of first semiconductor layers comprising wide bandgap semiconductor layers, a narrow bandgap semiconductor layer, and a chirp layer between the plurality of first semiconductor layers and the narrow bandgap semiconductor layer. The values of overlap integrals between different electron wavefunctions in a conduction band of the chirp layer can be less than 0.05 for intersubband transition energies greater than 1.0 eV, and/or the values of overlaps between electron wavefunctions and barrier centers in a conduction band of the chirp layer can be less than 0.3 nm?1, when the structure is biased at an operating potential. The chirp layer can comprise a short-period superlattice with alternating wide bandgap barrier layers and narrow bandgap well layers, wherein the thickness of the barrier layers, or the well layers, or the thickness of both the barrier and well layers changes throughout the chirp layer.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a microelectromechanical systems (MEMS) device. The method includes forming a filter stack over a carrier substrate. The filter stack comprises a particle filter layer having a particle filter. A support structure layer is formed over the filter stack. The support structure layer is patterned to define a support structure in the support structure layer such that the support structure has one or more segments. The support structure is bonded to a MEMS structure.

Abstract: A method of forming a high voltage optical transformer includes forming a via through a transparent carrier wafer, forming a conductive layer within the via, bonding a solid state lighting (SSL) package to a first side of the carrier wafer, and bonding a photovoltaic (PV) wafer to a second side of the carrier wafer opposite to the first side. The photovoltaic wafer may include an active area and a conductive area located outside of the active area that is in electrical contact with the conductive layer. The method further includes forming both an SSL contact with the solid state lighting package and a PV contact with the conductive layer on the same side of the carrier wafer.

Abstract: Provided is a quantum computing device and system. The quantum computing device includes a first qubit chip, a readout cavity structure surrounding a first end part of the first qubit chip, and a storage cavity structure surrounding a second end part of the first qubit chip, wherein the first qubit chip includes a first readout antenna disposed within the readout cavity structure, a first storage antenna disposed in the storage cavity structure, and a first qubit element provided between the first readout antenna and the first storage antenna, and wherein the first qubit element is disposed between the readout cavity structure and the storage cavity structure.

Abstract: A quantum device according to an example embodiment includes a quantum chip 10, and an interposer 20 on which the quantum chip 10 is mounted, in which the interposer 20 includes a conductive wiring line CL1 electrically connected to the quantum chip 10, a mounting surface 21 of the interposer 20 on which the quantum chip 10 is mounted or an opposite surface 22 opposite to the mounting surface 21 includes a first area AR11 and a second area AR12 different from the first area AR11 as viewed in a direction perpendicular to the mounting surface 21 or the opposite surface 22, the conductive wiring line CL1 is disposed in the first area AR11 on the mounting surface 21 or the opposite surface 22, and a movable member 60 is in contact with the second area AR12 of the interposer 20.

Abstract: A semiconductor device includes a peripheral circuit region with a first substrate, circuit devices on the first substrate, and a first wiring structure, a memory cell region with a second substrate that has a first region and a second region, gate electrodes stacked in the first region, channel structures that penetrate the gate electrodes, a first horizontal conductive layer on the second substrate in the first region, an insulating region on the second substrate in the second region, a second horizontal conductive layer on the first horizontal conductive layer and the insulating region, and a second wiring structure, and a third wiring structure that connects the first substrate to the second substrate, and includes an upper via that penetrates the second horizontal conductive layer, the insulating region, and the second substrate, and a lower wiring structure connected to the upper.

Abstract: Techniques regarding encapsulating one or more superconducting devices of a quantum processor are provided. For example, one or more embodiments described herein can regard a method that can comprise depositing a metal fluoride layer onto a superconducting resonator and a silicon substrate that can be comprised within a quantum processor. The superconducting resonator can be positioned on the silicon substrate. Also, the metal fluoride layer can coat the superconducting resonator.

Abstract: Quantum processors having qubits with tunable capacitance are provided. The qubits include Josephson junctions shunted by capacitors and are tunably coupled to capacitance loops such that the resonant frequencies of the qubits and capacitance loops avoid entanglement with each other. Methods for tuning the capacitance of such qubits by varying the coupler's coupling strength are provided. These methods include methods for calibrating qubits' capacitance.

Abstract: Techniques for quantum error correction of a multi-level system are provided and described. In some aspects, techniques for encoding a state of a multi-level quantum system include encoding a quantum information in a two-mode state of two quantum mechanical oscillators. Techniques for protecting the two-mode state against dephasing and energy loss are described.

Abstract: A quantum processing unit is disclosed. The quantum processing unit includes at least one superconducting qubit that is based on phase-biased linear and non-linear inductive-energy elements. A superconducting phase difference across the linear and non-linear inductive-energy elements is biased, for example, by an external magnetic field, such that quadratic potential energy terms of the linear and non-linear inductive-energy elements are cancelled at least partly. In a preferred embodiment, such cancellation is at least 30%. The partial cancellation of the quadratic potential energy terms makes it possible to implement a high-coherence high-anharmonicity superconducting qubit design.

Abstract: A method for etching a hardmask layer includes forming a photoresist layer comprising an organometallic material on a hardmask layer comprising a metal-containing material, exposing the photoresist layer to ultraviolet radiation through a mask having a selected pattern, removing un-irradiated areas of the photoresist layer to pattern the photoresist layer, forming a passivation layer comprising a carbon-containing material selectively on a top surface of the patterned photoresist layer, and etching the hardmask layer exposed by the patterned photoresist layer having the passivation layer formed thereon.

Abstract: Provided herein are metal structures that may include a cobalt alloy, a nickel alloy, or nickel, as well as related devices and methods. The metal structures may be formed by chemical vapor deposition (CVD), and may include trace amounts of precursor materials used during the CVD process.

Abstract: A quantum computing (QC) system that includes a plurality of qubits arranged substantially in a plurality of substantially planar regions that are substantially parallel to one another, at least some of the substantially planar regions including two or more qubits and one or more qubits of each substantially planar region configured to interact with one or more qubits of at least one other substantially planar region.

Abstract: Systems, computer-implemented methods, and techniques facilitating antenna-based thermal annealing of qubits are provided. In one example, a first antenna can be positioned above a superconducting qubit chip having a first Josephson junction and a second Josephson junction. The first antenna can direct a first electromagnetic wave toward the first Josephson junction. A first length of a first defined vertical gap, between the first antenna and the superconducting qubit chip, can be sized to cause the first electromagnetic wave to circumscribe a first set of one or more capacitor pads of the first Josephson junction, thereby annealing the first Josephson junction, without annealing the second Josephson junction. In another example, the first length of the first defined vertical gap can be a function of a model of the first electromagnetic wave as a cone, wherein the cone originates from the first antenna and extends toward the superconducting qubit chip.

Abstract: A superconducting complex quantum computing circuit includes a circuit substrate in which a wiring pattern of a circuit element including quantum bits and measurement electrodes, and ground patterns are formed, and through-electrodes connecting the ground pattern formed on a first surface of the substrate surface and the ground pattern formed on a second surface; a first ground electrode including a first contact portion in contact with the ground patterns, and a first non-contact portion having a shape corresponding to a shape of the wiring pattern; a second ground electrode including a second contact portion in contact with the ground pattern; a control signal line provided with a contact spring pin at a tip; and a pressing member that presses the first ground electrode against the first surface of the circuit substrate or presses the second ground electrode against the second surface of the circuit substrate.

Abstract: A monofilament (100) for producing an Nb3Sn-containing superconductor wire (33) includes a powder core (1) with an Sn-containing powder, a reaction tube (3) composed of an Nb alloy that includes Nb and at least one further alloy component X. The powder core is disposed within the reaction tube. The monofilament also includes at least one source (4) for at least one partner component Pk. A respective source includes one or more source structures at a unitary radial position in the monofilament. The alloy component X and the partner component Pk form precipitates XPk on reaction annealing of the monofilament in which Sn from the powder core and Nb from the reaction tube react to produce Nb3Sn. The powder core is disposed in a moderation tube, which in turn is disposed within the reaction tube. This provides a monofilament for a powder-in-tube based Nb3Sn-containing superconductor wire with improved current carrying capacity.