Patents Examined by Matthew Smith
  • Patent number: 9646917
    Abstract: A component such as an interposer or microelectronic element can be fabricated with a set of vertically extending interconnects of wire bond structure. Such method may include forming a structure having wire bonds extending in an axial direction within one of more openings in an element and each wire bond spaced at least partially apart from a wall of the opening within which it extends, the element consisting essentially of a material having a coefficient of thermal expansion (“CTE”) of less than 10 parts per million per degree Celsius (“ppm/° C.”). First contacts can then be provided at a first surface of the component and second contacts provided at a second surface of the component facing in a direction opposite from the first surface, the first contacts electrically coupled with the second contacts through the wire bonds.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: May 9, 2017
    Assignee: Invensas Corporation
    Inventors: Rajesh Katkar, Cyprian Emeka Uzoh
  • Patent number: 9269776
    Abstract: A semiconductor device comprises a base substrate, a pattern on the base substrate, a buffer layer on the base substrate, and an epitaxial layer on the buffer. The pattern is a self-assembled pattern. A method for growing a semiconductor crystal comprises cleaning a silicon carbide substrate, forming a self-assembled pattern on the silicon carbide substrate, forming a buffer layer on the silicon carbide substrate, and forming an epitaxial layer on the buffer layer. A semiconductor device comprises a base substrate comprising a pattern groove and an epitaxial layer on the base substrate. A method for growing a semiconductor crystal comprises cleaning a silicon carbide substrate, forming a self-assembled projection on the silicon carbide substrate, forming a pattern groove in the silicon carbide, and forming an epitaxial layer on the silicon carbide.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: February 23, 2016
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Moo Seong Kim, Yeong Deuk Jo, Chang Hyun Son, Bum Sup Kim
  • Patent number: 8445904
    Abstract: The invention relates to transparent rectifying contact structures for application in electronic devices, in particular appertaining to optoelectronics, solar technology and sensor technology, and also a method for the production thereof. The transparent rectifying contact structure according to the invention has the following constituents: a) a transparent semiconductor, b) a transparent, non-insulating and non-conducting layer composed of metal oxide, metal sulphide and/or metal nitride, the resistivity of which is preferably in the range of 102 ?cm to 107 ?cm and c) a layer composed of a transparent electrical conductor wherein the layer b) is formed between the semiconductor a) and the layer c) and the composition of the layer b) is defined in greater detail in the description of the patent.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: May 21, 2013
    Assignee: Universität Leipzig
    Inventors: Marius Grundmann, Heiko Frenzel, Alexander Lajn, Holger von Wenckstern
  • Patent number: 8436402
    Abstract: An exposure mask according to an embodiment of the invention includes a first transmission region where a plurality of dots through which light is shielded or transmitted are arrayed into a matrix form having rows and columns and a second transmission region where a plurality of dots through which the light is shielded or transmitted are arrayed into a matrix form having rows and columns and is disposed adjacent to the first transmission region. The dots arrayed in a row or a column of the first transmission region, which is adjacent to the second transmission region, have an area intermediate between areas of dots arrayed on both sides of the row or the column.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: May 7, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ken Tomita
  • Patent number: 8426728
    Abstract: Solar cells and methods for manufacturing solar cells and/or components or layers thereof are disclosed. An example method for manufacturing a multi-bandgap quantum dot layer for use in a solar cell may include providing a first precursor compound, providing a second precursor compound, and combining a portion of the first precursor compound with a portion of the second precursor compound to form a multi-bandgap quantum dot layer that includes a plurality of quantum dots that differ in bandgap.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: April 23, 2013
    Assignee: Honeywell International Inc.
    Inventors: Linan Zhao, Zhi Zheng, Marilyn Wang, Xuanbin Liu, Huili Tang
  • Patent number: 8426251
    Abstract: A method of manufacturing a semiconductor device includes providing a carrier and attaching a plurality of semiconductor chips to the carrier. The semiconductor chips have a first electrode pad on a first main face and at least a second electrode pad on a second main face opposite to the first main face, whereby the first electrode pad is electrically connected to the carrier. A plurality of first bumps are formed on the carrier, the first bumps being made of a conductive material. The carrier is then singulated into a plurality of semiconductor devices, wherein each semiconductor device includes at least one semiconductor chip and one first bump.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: April 23, 2013
    Assignee: Infineon Technologies AG
    Inventor: Horst Theuss
  • Patent number: 8420555
    Abstract: A manufacturing method for a semiconductor device including: determining pattern dependency of a radiation factor of an element forming surface of one wafer having a predetermined pattern formed on the wafer; determining a heating surface of the wafer, based on the pattern dependency of the radiation factor; holding the one wafer having the determined heating surface and another wafer having a determined heating surface, spaced at a predetermined distance in such a manner that non-heating surfaces of the one wafer and the another wafer oppose to each other; and heating the each heating surface of the one wafer and the another wafer.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: April 16, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaki Kamimura, Kenichi Yoshino
  • Patent number: 8420437
    Abstract: Disclosed is a method for forming an EMI shielding layer on all surfaces of a semiconductor package in order to enhance EMI shielding effect on all surfaces and to prevent electrical short to external terminals of the semiconductor package. According to the method, a temporary protective layer is formed on the external terminals where the temporary protective layer is further in contact with a plurality of annular surface regions of the semiconductor package surrounding and adjacent to the external terminals. Then, the EMI shielding layer is formed on the top surface, the bottom surface and the side surfaces of the semiconductor package without forming on the external terminals.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: April 16, 2013
    Assignee: Powertech Technology Inc.
    Inventor: Wen-Jeng Fan
  • Patent number: 8415251
    Abstract: A method for producing an electrical component (1) is proposed, in which a ceramic base body (5) that contains a through-hole contact (10) and at least one metallization surface (20C) electroconductively connected to the through-hole contact is provided in a method step A). On the surface of the base body, an electrically insulating first material is arranged in layer form at least above the through-hole contact in method step B), and thereafter an electrically conductive second material is applied above through-hole contact (10) in method step C). Then a solder contact (30B) that electroconductively connects through-hole contact (10) through passivation layer (25B), which is formed from the first material by sintering, is formed by hardening in method step D).
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: April 9, 2013
    Assignee: EPCOS AG
    Inventors: Sebastian Brunner, Thomas Feichtinger, Günter Pudmich, Horst Schlick, Patrick Schmidt-Winkel
  • Patent number: 8395166
    Abstract: Disclosed herein is a light emitting diode. The light emitting diode includes a support substrate, semiconductor layers formed on the support substrate, and a metal pattern located between the support substrate and the lower semiconductor layer. The semiconductor layers include an upper semiconductor layer of a first conductive type, an active layer, and a lower semiconductor layer of a second conductive type. The semiconductor layers are grown on a sacrificial substrate and the support substrate is homogeneous with the sacrificial substrate.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: March 12, 2013
    Assignee: Seoul Opto Device Co., Ltd.
    Inventors: Won Cheol Seo, Chang Youn Kim, Yeo Jin Yoon
  • Patent number: 8390131
    Abstract: A semiconductor device that includes an electrode of one material and a conductive material of lower resistivity formed over the electrode and a process for fabricating the semiconductor device.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: March 5, 2013
    Assignee: International Rectifier Corporation
    Inventors: Sven Fuchs, Mark Pavier
  • Patent number: 8372722
    Abstract: A method of fabricating semiconductor device includes forming a recess having a substantially rectangular section and forming an oxide layer on sidewalls and an oxide layer on a bottom of the recess by anisotropic oxidation, wherein the oxide layer on the sidewalls is thinner than the oxide layer on the bottom of recess. The method further includes completely removing the oxide layer on the sidewalls and partially removing the oxide layer on the bottom of the recess. The method also includes performing an orientation selective wet etching on the recess using a remaining oxide layer of the recess as a stop layer to shape the sidewalls into a ? shaped section. The method includes removing the remaining oxide layer using an isotropic wet etching.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: February 12, 2013
    Assignee: Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Qingsong Wei, Yonggen He, Huanxin Liu, Jialei Liu, Chaowei Li
  • Patent number: 8263479
    Abstract: Multiphoton absorption is generated, so as to form a part which is intended to be cut 9 due to a molten processed region 13 within a silicon wafer 11, and then an adhesive sheet 20 bonded to the silicon wafer 11 is expanded. This cuts the silicon wafer 11 along the part which is intended to be cut 9 with a high precision into semiconductor chips 25. Here, opposing cut sections 25a, 25a of neighboring semiconductor chips 25, 25 are separated from each other from their close contact state, whereby a die-bonding resin layer 23 is also cut along the part which is intended to be cut 9. Therefore, the silicon wafer 11 and die-bonding resin layer 23 can be cut much more efficiently than in the case where the silicon wafer 11 and die-bonding resin layer 23 are cut with a blade without cutting a base 21.
    Type: Grant
    Filed: September 11, 2003
    Date of Patent: September 11, 2012
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Fumitsugu Fukuyo, Kenshi Fukumitsu, Naoki Uchiyama, Ryuji Sugiura
  • Patent number: 8158517
    Abstract: An object of the present invention is to provide a method for manufacturing a display device by improving the utilization efficiency of materials and simplifying manufacturing process. Another object of the invention is to provide a technique for forming a pattern such as a wiring having a predetermined shape included in a display device with good controllability. A method for manufacturing a wiring substrate of the invention includes the steps of: forming a first region having a subject material; modifying the surface of the subject material partly to form a second region having a boundary with respect to the first region; continuously discharging a composition containing a conductive material to a part of the first region across the boundary and the second region; solidifying the composition to form a conductive layer; and removing the conductive layer formed in a part of the first region across the boundary.
    Type: Grant
    Filed: June 22, 2005
    Date of Patent: April 17, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroko Yamamoto, Ryo Tokumaru
  • Patent number: 8143148
    Abstract: A method for forming a laser diode structure. The method includes providing a laser diode material having a surface region. A multilayer dielectric mask structure comprising alternating first and second dielectric layers is formed overlying the surface region. The method forms a laser diode structure using the multilayer dielectric mask structure as a mask. The method selectively removes a portion of the first dielectric layer to form one or more undercut regions between the second dielectric layers. A passivation layer overlies the multilayer dielectric mask structure and the undercut region remained intact. The dielectric mask structure is selectively removed, exposing a top surface region of the laser diode structure. A contact structure is formed overlying at least the exposed top surface region.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: March 27, 2012
    Assignee: Soraa, Inc.
    Inventors: James W. Raring, Daniel F. Feezell, Nick Pfister
  • Patent number: 8120122
    Abstract: A method of forming a pattern includes forming a first layer on a substrate, forming a second layer on the first layer, depositing a multi-temperature phase-change material on the second layer, patterning the second layer using the multi-temperature phase-change material as a mask, reflowing the multi-temperature phase-change material, and patterning the first layer using the reflowed multi-temperature phase-change material as a mask.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: February 21, 2012
    Inventor: Scott Jong Ho Limb
  • Patent number: 8105879
    Abstract: Flip chip ball grid array semiconductor devices and methods for fabricating the same. In one example, a near chip scale method of semiconductor die packaging may comprise adhering the die to a substrate in a flip chip configuration, coating the die with a first polymer layer, selectively removing the first polymer layer to provide at least one opening to expose a portion of the die, and depositing a first metal layer over the first polymer layer, the first metal layer at least partially filling the at least one opening to provide an electrical contact to the die, and including a portion that substantially surrounds the die in a plane of an upper surface of the first metal layer to provide an electromagnetic shield around the die.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: January 31, 2012
    Assignee: Skyworks Solutions, Inc.
    Inventors: David J Fryklund, Alfred H Carl, Brian P Murphy
  • Patent number: 8101449
    Abstract: A process for altering the thermoelectric properties of an electrically conductive material is provided. The process includes providing an electrically conducting material and a substrate. The electrically conducting material is brought into contact with the substrate. A thermal gradient can be applied to the electrically conducting material and a voltage applied to the substrate. In this manner, the electrical conductivity, the thermoelectric power and/or the thermal conductivity of the electrically conductive material can be altered and the figure of merit increased.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: January 24, 2012
    Assignees: Toyota Motor Engineering & Manufacturing North America, Inc., University of California, Berkeley
    Inventors: Wenjie Liang, Allon Hochbaum, Melissa Fardy, Minjuan Zhang, Peidong Yang
  • Patent number: 8093126
    Abstract: A nonvolatile semiconductor memory device includes a gate portion formed by laminating a tunnel insulating film, floating gate electrode, inter-poly insulating film and control gate electrode on a semiconductor substrate, and source and drain regions formed on the substrate. The tunnel insulating film has a three-layered structure having a silicon nitride film sandwiched between silicon oxide films. The silicon nitride film is continuous in an in-plane direction and has 3-coordinate nitrogen bonds and at least one of second neighboring atoms of nitrogen is nitrogen.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: January 10, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuuichiro Mitani, Daisuke Matsushita, Ryuji Ooba, Isao Kamioka, Yoshio Ozawa
  • Patent number: 8093128
    Abstract: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: January 10, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: William W. C. Koutny, Jr., Sam Geha, Igor Kouznetsov, Krishnaswamy Ramkumar, Fredrick B. Jenne, Sagy Levy, Ravindra Kapre, Jeremy Warren