Abstract: A modification method and system. The method includes detecting and monitoring by a computing system, a frequency signal associated with an input voltage signal used for powering a plurality of power consumption devices at a specified location. The computing system compares the frequency signal to a predetermined frequency value. The computing system determines that the frequency signal comprises a first value that is not equal to the predetermined frequency value. The computing system calculates a difference value between the first value and the predetermined frequency value. The computing system compares the difference value to a second value. The computing system enables a load adjustment modification process associated with the plurality of power consumption devices. The computing system generates and stores a report associated with the load adjustment modification process.

Abstract: A load management method and system. The method includes detecting and monitoring by a computing system, a frequency signal associated with an input voltage signal used for powering computing apparatuses at a specified location. The computing system compares the frequency signal to a predetermined frequency value. The computing system determines that the frequency signal comprises a first value that is not equal to the predetermined frequency value. The computing system calculates a difference value between the first value and the predetermined frequency value. The computing system compares the difference value to a second value and analyzes a power demand profile. The computing system enables a load adjustment modification process associated with the plurality of power consumption devices based on the difference value and the power demand profile. The computing system generates and stores a report associated with the load adjustment modification process.

Abstract: An apparatus for transmitting data across a high-speed serial bus includes an IEEE 802.3-compliant PHY having a GMII interface; an IEEE 1394-compliant PHY in communication with the IEEE 802.3-compliant PHY via a switch; the switch determining whether data transmission is be routed to the IEEE 802.3-compliant PHY or the IEEE 1394-compliant PHY; a first connection, the first connection for transmitting data between a device and the IEEE 802.3-compliant PHY; and a second connection, the second connection for transmitting data between a device and the IEEE 1394-compliant PHY.

Abstract: An arbitrator circuit for accessing a bus comprises a logic gate arrangement (406), one input of which is coupled to a first bus line. The circuit comprises a switching arrangement (404, 405, 407). As a response to a control signal the switching arrangement disconnects a first half (402) of the first bus line from a second half (403), and couples the second half (403) to a first fixed potential. A second bus line (401) is decoupled from the logic gate arrangement (406), which is coupled to receive a second fixed potential. The second bus line is coupled to the first fixed potential. Two sources are available for providing the control signal to the switching arrangement (404, 405, 407). One of them is the output of the logic gate arrangement (406).

Abstract: A network signal processing circuit includes a first signal processing module, a first sampling rate converter, a second signal processing module, a second sampling rate converter and a timing controller. The first signal processing module is utilized for processing a network signal to output a first processed signal. The first sampling rate converter is utilized for performing signal frequency conversion on the first processed signal according to a first clock timing adjusting signal and outputting a first converted signal. The second signal processing module is utilized for processing the first converted signal to output a second processed signal. The second sampling rate converter is utilized for performing signal frequency conversion on the second processed signal according to a second clock timing adjusting signal and outputting a second converted signal. The timing controller is utilized for generating the first and second clock timing adjusting signals.

Abstract: The USB interface data transmission device comprises a USB interface controller unit, a dynamic data transmission unit, a central controller unit, a transmission mode configuration unit, a driver program memory and a data transmission interface. In them: The dynamic data transmission unit includes a data input node and a data output node, wherein the data input node supports the data downloading and the data output node support the data uploading, while when necessary the data input node and the data output node support each other's functions by changing their respective data uploading and downloading functions. In a download mode both the data input node and the data output node support the data downloading operation and in an upload mode both support the data uploading operation.

Abstract: A peer-to-peer special purpose processor architecture and method is described. Embodiments include a plurality of special purpose processors coupled to a central processing unit via a host bridge bus, a direct bus directly coupling each of the plurality of special purpose processors to at least one other of the plurality of special purpose processors and a memory controller coupled to the plurality of special purpose processors, wherein the at least one memory controller determines whether to transmit data via the host bus or the direct bus, and whether to receive data via the host bus or the direct bus.

Abstract: An electronic device, comprising a USB connector through which another electronic device is connected to the electronic device; and a power supply circuit that supplies power from a power source to the other electronic device via a specified pin other than a power supply pin of the USB connector.

Abstract: An information processing apparatus and method include mode controlling. A first information processing unit controls a telephone process using a radio communication unit and displays the image to display unit in response to a request, and a second information processing unit mutually operable in parallel with the first information processing unit controls a telephone process using the radio communication unit and makes the display unit display the image in response to a request. The mode controlling sets one of the first information processing unit and the second information processing unit to a master mode and sets other of the first information processing unit and the second information processing unit to a slave mode.

Abstract: The network node includes a local crystal oscillator for providing a time reference derived from the clock signal produced by the local crystal oscillator, a reset stage for resetting the network node in response to a bus reset pulse received through the network and a control means for issuing a bus reset pulse of a predetermined length substantially greater than a clock period of the clock signal of the local crystal oscillator. Further the network node includes a bus reset detector for determining a length of the received bus reset pulse based on the local time reference. The bus reset detector in the network node is also adapted to adjust the local time reference based on the determined length of the received bus reset pulse.

Abstract: A microprocessor that performs adaptive power throttling includes a calculation unit that calculates an average power consumed by the microprocessor over a most recent predetermined sample time and determines whether the average power is less than a predetermined maximum power value. A power management unit controls the microprocessor to conditionally operate at a predetermined frequency if the average power is less than the predetermined maximum power value. The predetermined frequency is a frequency at which the microprocessor may consume more than the predetermined maximum power value. The predetermined maximum power value and sample time are specified to achieve power and/or thermal design goals of a system in which the microprocessor operates. The predetermined maximum power and/or sample time values are programmable by system software.

Abstract: Technologies are described herein for intentionally allowing errors in a computational system to optimize energy consumption of the computational system. A cost-benefit analysis is performed to identify one or more allowable errors and one or more non-allowable errors in the computational system. The allowable errors may be identified by the cost-benefit analysis as being acceptable errors for optimizing energy consumption with respect to accuracy of the computational system. The non-allowable errors may be identified by the cost-benefit analysis as being unacceptable errors for optimizing energy consumption with respect to accuracy of the computational system. The computational system is transformed from a first state in which the computational system corrects or prevents the allowable errors and the non-allowable errors into a second state in which the computational system allows the allowable errors and corrects or prevents the non-allowable errors.

Abstract: Method, system and apparatus enabling a computing system to automatically identify the capabilities of a power supply coupled to the computing system. The power supply includes a controller that sends an identification code to a computing system prior to sending a power good signal to the computing system. The identification code and the power good signal are preferably sent over a single conductor, such as a power supply connector pin. The computing system receives the identification code for cross-referencing against a list of power supply identification codes and associated capabilities. Optionally, instructions from the computer system to an output device may be controlled as a function of the identified power supply capabilities.

Abstract: An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced.

Abstract: A storage management server collects, stores and displays positions, temperatures and temperature threshold values of physical storage devices from a storage apparatus. It collects, stores and displays positions and power consumptions of variable factor generation sources which are factors that cause the physical storage devices to vary in operation environments, and also calculates the influenceability by variable factor generation sources against the physical storage devices and affected temperatures thereof. It compares the temperature of a given physical storage device to a temperature threshold value of this physical storage device or compares it to an affected temperature thereof due to the variable factor generation sources, thereby moving, for data transfer, an operation position of physical storage device based on a comparison result at such time.

Abstract: In accordance with an aspect of the present invention, a corresponding list of muxes is maintained for each combination of a peripheral and a mux option. The list is then retrieved to program the required muxes to connect the communication paths from a peripheral on the corresponding mux option, based on which the list is retrieved. In an embodiment, the information is maintained in the form of a table, with each entry storing the data corresponding to a mux and mux option. The entries are linked by appropriate pointers to form the linked list.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.

Abstract: The present invention is a submarine mast antenna controller for controlling a plurality of functions performed by an antenna mast of a submarine. The submarine mast antenna controller is a solid state electronic control unit on a single card that monitors various submarine mast antenna system sensors and motors, and controls electromechanical devices associated with the sensors and improves functionality over the former ACU system by consolidating control interfaces and indicators in one computer terminal via a VXI interface.

Abstract: An information handling system includes at least two processing systems that share system resources. In response to detecting a designated event, a power control module of the information handling system can select one of a plurality of available power profiles. The power profile can be selected based on the event and state information indicative of a state of the processing systems. Based on the selected profile, the power control module can set an operational power mode of one or more of the shared system resources.

Abstract: A host device and a storage device with a Serial ATA (SATA) architecture to independently transition to a deeper low power state after first entering an initial low power state without first transitioning to the Active state. The transition from the Partial state to the Slumber state is direct and the transition may be enabled, but not negotiated through a handshaking process.