Abstract: The invention provides a voltage-controlled device, method and computer device capable of dynamically regulating voltage and effectively saving energy. The voltage-controlled device receives a VID from a CPU, determines a core voltage according to a load line defined therein, and supplies the core voltage to the CPU. The voltage-controlled device has a load line register set and a write logic. The load line register set has a plurality of registers, and the values of which represent the defined load line. The write logic changes the values of the registers in the load line register set according to a write signal.

Abstract: A metering system configured to couple to multiple specialty systems, such as a control system. At least some of the illustrative embodiments are processing units comprising a processor, a memory coupled to the processor, and a communication port configured to coupled to a backbone communication network of a control system. The memory stores a program that causes the processor to selectively participate (over the communication port) as a processing unit of a control system of a first manufacturer (the control system implements a first proprietary communication protocol between processing units), and to participate (over the communication port) as a processing unit of a control system of a second manufacturer different than the first manufacturer (the control system of the second manufacturer implements a second proprietary communication protocol between the processing units).

Abstract: One embodiment of the present invention provides a system that augments a circuit design with a mechanism for detecting and correcting timing errors. This system first partitions the circuit into a set of blocks that are clocked by an independent clock source, and integrates an error signal propagation circuit between the set of blocks. For a respective block, the system determines a set of internal registers that are to be implemented as double data sampling registers, and replaces the determined set of internal registers with double data sampling registers, wherein a given double data sampling register is configured to generate an error signal when it detects a timing error. Then, the system integrates a two-phase error correction circuit into the respective block, wherein when notified of a timing error by a double data sampling register, the two-phase error correction circuit is configured to stall registers in the respective block.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device determines whether to initialize to a standard protocol or to an advanced protocol. Upon determining to initialize to the advanced protocol, the second remote device then waits for a synchronization point sequence.

Abstract: A mechanism for controlling the hardware resources on a blade server, and thereby limiting the power consumption of the blade server is disclosed. The enforceable hardware resources that are controlled include the base frequency of the central processing unit (CPU) as well as power to individual banks of physical memory, for example dual-inline memory modules (DIMMs). The hardware resources are tuned in dependence on actual server utilization such that applications running on the blade only have the allocated hardware resources available to them. Deactivated hardware resources are powered off and are so ‘hidden’ from the operating system when they are not required. In this manner, power consumption in the entire chassis can be managed such that all server blades can be powered on and operate at higher steady-state utilization. The utilization of the powered on resources in a blade center is also improved.

Abstract: A computer system includes compute nodes coupled through a switch to shared or non-shared I/O devices. The switch includes a pool of bridge headers and virtual bridges coupling a root port of a compute node to each of one or more shared or non-shared I/O devices. The switch is configured to associate each of the virtual bridges with a respective one of the fixed pool of bridge headers, receive a packet including data identifying the root port and a shared or non-shared I/O device, and route the packet in response to comparing data in the packet to data in the bridge headers associated with the virtual bridges. The virtual bridges comprise a hierarchy of virtual bridges in which one virtual bridge connects the root port to the remaining virtual bridges of the hierarchy. The switch may change the associations between virtual bridges and bridge headers.

Abstract: An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced.

Abstract: A processor local bus bridge for a processor block ASIC core for embedding in an IC is described. A core logic-to-core logic bridge includes a slave processor local bus interface, a crossbar switch coupled to the slave processor local bus interface and a master processor local bus interface coupled to the crossbar switch. The slave processor local bus interface and the master processor local bus interface are coupled to one another via the crossbar switch for bidirectional communication between a first and a second portion of core logic. The bridge provides rate adaptation for bridging for use of a frequency of operation associated with the crossbar switch which has substantially greater frequencies of operation than those associated with the core logic sides of the master and slave processor local bus interfaces.

Abstract: A test system for overclocking capability of a central processing unit (CPU) includes a basic input and output system (BIOS), a frequency generator, and a watchdog timer. The BIOS includes an input module, a watchdog control module, and a frequency increasing module. The input module inputs an initial frequency of a CPU to the frequency generator to adjust a real-time frequency of the CPU. The watchdog control module sends a counter signal to the watchdog timer in a preset time interval. The watchdog timer receives the counter signal. If the watchdog timer does not receive the counter signal within the preset time, the watchdog timer outputs a reset signal to restart the computer. The frequency increasing module adds a preset increment to the real-time frequency to obtain a newly adjusted frequency, and provides the newly adjusted frequency to the frequency generator to adjust the real-time frequency.

Abstract: A low-latency, peer-to-peer TDM bus including one or more data lines and one or more control lines is provided. Attached devices access the bus sequentially in order of their bus addresses. During a device's access period, if the device has data to transmit, the device places its address on the data lines, asserts a START signal on the bus, and proceeds to transmit data to the other devices on the bus. When the data transmission is completed, the device asserts an END signal on the bus, thus passing control of the bus to the next device in the sequence. If the device has no data to transmit, the device simply places its address on the data lines, asserts the START signal, and asserts the END signal, and control passes directly to the next device in line. In this manner, each device has an opportunity to transmit on the bus.

Abstract: A fault-tolerant RAID system is disclosed. The system includes redundant RAID controllers coupled by a PCI-Express link. When a PCI-Express controller of one of the RAID controllers receives a PCI-Express memory write request transaction layer packet (TLP), it interprets a predetermined bit in the header as an interrupt request flag, rather than as its standard function specified by the PCI-Express specification. If the flag is set, the PCI-Express controller interrupts the processor after storing the message in the payload at the specified memory location. In one embodiment, an unused upper address bit in the header is used as the interrupt request flag. Additionally, unused predetermined bits in the TLP header are used as a message tag to indicate one of a plurality of message buffers on the receiving RAID controller into which the message has been written. The PCI-Express controller sets a corresponding bit in a register to indicate which message buffer was written.

Abstract: A method, system, and article of manufacture for processing virtual interrupts in a logically partitioned system are provided. An intelligent virtual global interrupt queue (virtual GIQ) that may be associated with a plurality of virtual processors running in a logical partition may be utilized. Upon receiving a virtual interrupt, the virtual GIQ may examine the operating states of the associated virtual processors. In an effort to ensure the virtual interrupt is processed as quickly as possible, the virtual GIQ may present the virtual interrupt to one of the associated virtual processors determined to be in an operating state best suited for processing the virtual interrupt.

Abstract: A method for designing an integrated circuit where the integrated circuit includes a plurality of modules and where each module includes an initiator port and a target port coupled to a distributed routing network. The initiator port is implemented by configuring whether the initiator or the distributed routing network is responsible for ordering responses to requests issued by the initiator port and defining the maximum number of requests that are permitted to be outstanding at the same time. The initiator port is further configured to define whether a delay stage is required in said initiator port. The distributed routing network is defined by the number of routing resources between the initiator and the target, an arbitration method for arbitrating between requests and an association between the routing resources and the targets.

Abstract: A method of performing a VMEbus split-read transaction (701) includes providing a master VMEbus module (502) coupled to a slave VMEbus module (504) through a VMEbus network (506). The master VMEbus module initiates a VMEbus split-read transaction request (524) in a VME address encoding phase (601) to the slave VMEbus module, where the VMEbus split-read transaction request comprises a return address (660) for the VMEbus master module in the VMEbus address encoding phase, and where the VMEbus split-read transaction request requests a set of data (544). The master VMEbus module releases the VMEbus network and the slave VMEbus module acquires the VMEbus network. The slave VMEbus module places the set of data on the VMEbus network, where the set of data comprises the return address for the VMEbus master module, and the master VMEbus module retrieves the set of data.

Abstract: A bus master 2, 4 sends write transactions to a bus slave 8 which include separate write addresses AW and write data WD. Write transaction identifiers AWID, WID are associated with these write addresses and write data. The bus slave can accept multiple write addresses such that there can be copending write transactions to the same bus slave. The bus slave uses the write transaction identifiers to correlate interleaved write data for the co-pending write transactions with their write addresses.

Abstract: Methods and apparatuses are disclosed for providing a bus in a computer system. In one embodiment, an apparatus comprises: a central processing unit (CPU), a bridge coupled to the CPU, a first slot configured to receive a device, where a first portion of the bridge is coupled to the first slot, a second slot configured to receive a device, where a second portion of the bridge is coupled to the second slot, and where inserting a jumper board into the first slot couples the first portion of the bridge to the second slot.

Abstract: A portable storage device 10 includes a body 12, an actuator 16, and an indicator 18. When coupled to a host device 22, a user depressing the actuator 16 causes an interrupt message to be sent to the host device, which initiates shutdown of the portable device by removing it from a host device list of available storage media, and de-powers the portable device. The indicator then changes to signify that it is safe to remove the portable device from the host. The indicator may be visual, aural, or tactile. Preferably, the indicator uniquely identifies four states regarding the status of computer instruction exchange between the portable and host devices, including normal and inactive, normal and active, error, and ready-to-be-removed states. The latter is available only after actuating the actuator. Removal of the portable device is thereby effected by a single user action at the portable device: depressing the actuator.

Abstract: In an advanced microcontroller bus architecture (AMBA) system with reduced power consumption, a signal transition is allowed to occur only in loads required for transferring bus signals by isolating loads on a bus signal transfer path requiring the signal transition from the other loads, so that the power consumption can be reduced in a bus architecture such as an advanced high-performance system bus (AHB).

Abstract: A method and apparatus for deterministic removal and reclamation of work items from an expansion bus schedule are disclosed herein. A work item is removed from an enabled expansion bus schedule data structure and a coherency signal is then generated utilizing an expansion bus host controller. The work item is then reclaimed in response to the generation of the coherency signal. In one embodiment, the enabled expansion bus schedule data structure is a Universal Serial Bus (USB) asynchronous schedule including a plurality of queue heads.

Abstract: An interface operates at an operating frequency. The interface includes transmitters and receivers that operate within the operating frequency of the interface. The interface also includes circuit elements to allow transmission of signals across the interface in which the signals have a frequency lower than the operating frequency of the interface.