Abstract: Certain embodiments of the invention may be found in a method and system for monitoring a set of semaphore registers using a limited-width test bus. Each semaphore register represents a separate hardware resource. The bits in a semaphore register are monitored jointly to determine whether the hardware resource it represents is in use by a software thread. The bits in the same register bit location of all the semaphore registers are monitored jointly to determine the ID number of the software thread currently using the hardware resource. The limited-width test bus comprises of bit lines representing each semaphore registers and bit lines representing the contents of the semaphore registers. Semaphore protocol steps are used in addition to changes monitored by the limited-width test bus to determine current usage of each hardware resource and to identify the ID number of the software thread using a hardware resource.

Abstract: Disclosed are ways of providing a highly flexible high availability storage system. Disk drive carriers for insertion into enclosures in a storage system include several disk drives. The enclosures accept carriers that include drives of different sizes, and drives compatible with different storage technologies, for instance Fibre Channel, SATA, or SAS. Drives oriented in their carriers in a manner that allows them to be connected to a common medium via identical flex circuits that are configured based on the orientation of the drives. Redundant controllers include redundant serial buses for transferring management information to the carriers. The carriers include a controller for monitoring the multiple serial buses and producing storage technology specific management commands for the disk drives.

Abstract: An edge detecting circuit detects an input level change (edge) of a synchronous signal provided from a synchronous signal input terminal. A data latch unit latches digital data provided from an external data input terminal. An address generating circuit provides an address signal. A write control unit activates/deactivates a write enable signal for writing to a RAM. An arbitration circuit monitors a write control enable signal, a read enable signal and a write enable signal, and detects a cycle, in which a CPU does not access the RAM.

Abstract: An interface connectable as a default host to a peripheral or as a default peripheral to a host, for serial data communication between host and peripheral during a session, and comprising: automated means for periodically checking a connection by periodically starting a session when connected as a default host and automated means for periodically checking a connection by periodically requesting a session when connected as a default peripheral.

Abstract: A semiconductor device in which input terminals for external interrupts can be set as desired. A plurality of external input terminals can be specified as interrupt terminals which output an input signal to an external interrupt circuit via an interrupt terminal selector. A selection control circuit specifies whether a plurality of external input terminals are used as interrupt terminals. According to the selection control circuit, the interrupt terminal selector outputs to the external interrupt circuit an input signal entered from an external input terminal which is specified as an interrupt terminal out of the plurality of external input terminals.

Abstract: System for processing programmable buttons using system control interrupts in a portable device. The system comprises a programmable button that comprises logic to generate a selected system control interrupt when actuated. The system also comprises interrupt logic coupled to receive the selected system control interrupt. The interrupt logic comprises logic to generate a button report that includes a button identifier, which indicates that the programmable button has been actuated. The system also comprises button support logic that is coupled to receive the button report, the button support logic comprises logic to determine a selectable device function associated with the button identifier, and logic to activate the selectable device function.

Abstract: Switching method and apparatus for assigning a communication grant to a first processing unit in a communication network comprising a plurality of processing units, each processing unit being connected to each other processing unit of the plurality of processing units. The switching method includes steps of performing an identical arbitration procedure for a communication grant by each of the plurality of processing units, and switching at least one of the plurality of processing units according to the identical arbitration procedure.

Abstract: A method for generating interrupt commands for a microprocessor system includes storing interrupts in a pending interrupts register, and storing priority values associated with the stored interrupts in a plurality of priority registers coupled to the pending interrupts register. A plurality of counters coupled in cascade to the plurality of priority registers are loaded with the stored priority values. The loaded priority values are incremented at predetermined intervals, and are compared for identifying the interrupt having a highest priority. The method further includes identifying a respective interrupt service routine to be executed based upon the interrupt having the highest priority.

Abstract: A process of programming or reprogramming a reprogrammable onboard memory (5) comprises programming or reprogramming the onboard memory of several modules (M0, M1) in parallel through a multiple access bus (6) to which the modules are connected. In the case of blank flash memories, a process downloads code through the multiple access bus (6) and executes the code, eliminating all external constraints (such as frequency, binary throughput). The process is more particularly intended to apply to onboard flash type memories.

Abstract: A delay interval is calculated for a processor that attempts to reserve a reserved shared resource in a multiprocessing system. The delay interval is based on the relationship of a requesting processor and a reservation holding processor. Each delay interval is unique without consistent bias against a processor. The requesting processor queries the reservation status of a shared resource without invalidating an existing reservation. If a shared resource is reserved, the requesting processor waits for an amount of time corresponding to the delay interval before again attempting to reserve the shared resource. The present invention substantially reduces arbitration conflicts within multiprocessor systems.

Abstract: The method is provided for addressing the participants of a bus system comprising a control unit, a bus starting from the control unit and a plurality of participants connected to the bus. In the method, each participant not addressed so far feeds an identifying current for identification purposes into the bus, wherein all identifying currents flow through the bus towards the control unit. Each participant not addressed so far detects the current flowing through the bus. Only that participant not addressed so far, which does not detect any current or merely detects a current which is smaller than a predeterminable first threshold value, is identified as a participant not addressed so far. An address for addressing purposes is assigned to the participant thus identified. The aforementioned steps are carried out, without the respective participant addressed last, until all participants not addressed so far are addressed.

Abstract: A bus host designed to manage connection and disconnection of devices to and from a wired hub which includes a transceiver for wireless communication with wireless devices. The hub simulates wired connection in response to reception of a wireless signal from the wireless device.

Abstract: A data processing structure comprising a plurality of processors ad a data bus for a data communication with a serial data structure. The plurality of processors can be respectively coupled in parallel to the data bus, and a data communication via the data bus with one of the processors, preferably a programming of the processor, is authorized for the same, but is blocked for all of the other processors.

Abstract: Integrated pointing device and integrated keyboard inputs are accepted at a microcontroller that formats the inputs to the HID protocol and embeds the HID formatted inputs into SMBus messages for transfer over an SMBus to processing components of an information handling system. A state machine at the information handling system motherboard extracts the HID packets from the SMBus messages and provides the HID packets to HID registers for use by processing components. Keyboard and pointing device inputs communicated from integrated devices through an SMBus may be treated as trusted data separate from non-trusted inputs through external devices and buses.

Abstract: A memory system has a circuit board provided with a first slot connector into which a first memory module is inserted. A second slot connector is provided into which a second memory module is inserted. The first and the second memory modules are connected via a flexible bridge. The flexible bridge extends from respective ends of the memory modules opposite to that ends thereof which are inserted into the connector slots. The flexible bridge provides a signal bus between the memory modules.