Abstract: A method and structure for sensing data such as temperature with respect to objects such as silicon wafers undergoing fabrication or other processes involve the use of a monitor element of material and configuration similar to that of the objects being processed. A structure such as a closed loop or segment of a spiral may be formed on the surface of the monitor element, and acts as a secondary coil when brought into operative relation with a transformer structure which includes a primary coil, a current source and a sensing device. The sensing device senses variations in the electrical characteristics in the primary coil, caused by the presence of the monitor element, and can thereby determine the temperature or other desired data relating to the monitor element, which is substantially the same as comparable data for the objects being processed.
Type:
Grant
Filed:
September 20, 1993
Date of Patent:
November 14, 1995
Assignees:
AT&T Global Information Solutions Company, Hyundai Electronics America
Inventors:
James P. Yakura, Richard K. Cole, Matthew S. Von Thun, Crystal J. Hass, Derryl D. J. Allman
Abstract: A MOST capacitor for use in a DRAM is formed by using BPSG precipitates after densification as a mask for etching a BPSG layer to form BPSG islands. The BPSG islands are then used as a mask for etching a polysilicon layer to form pillars in the polysilicon layer.
Type:
Grant
Filed:
March 18, 1994
Date of Patent:
November 14, 1995
Assignee:
United Microelectronics Corporation
Inventors:
Water Lur, Jenn-Tarng Lin, Hsiaw-Sheng Chin
Abstract: A silicon oxide film is deposited on a substrate by chemical vapor deposition (CVD) using an organosilicon compound such as tetraethylorthosilicate (TEOS) and ozone as the principal reactants. The organosilicon compound gas and an ozone-oxygen gas which is relatively low in ozone concentration such as 0.1-1% are mixed in a gas mixer outside the CVD reaction chamber, and the resultant gas mixture is fed into the reaction chamber. Separately, another ozone-oxygen gas which is relatively high in ozone concentration such as 1-10% is introduced directly into the reaction chamber so as to come into contact with and mix with the aforementioned gas mixture in the vicinity of the substrate surface. The obtained silicon oxide film is good in film properties and step coverage, and the CVD operation does not suffer from deposition of reaction products in the gas feeding pipes and gas injecting nozzles.
Abstract: A method of suppressing adherence of silicon particles to IC bond pads, and corrosion thereof, during the dicing of silicon wafers by sawing. An anion of an organic acid is added to saw coolant water.
Type:
Grant
Filed:
May 26, 1994
Date of Patent:
October 24, 1995
Assignee:
Delco Electronics Corporatinon
Inventors:
Richard M. Sutherland, Howard E. Harrell, Wayne A. Sozansky, George C. Wolf
Abstract: A method of manufacturing a semiconductor device having a flat surface and an interlayer insulating film having superior crack resistance comprises forming a first silicon oxide film having a superior crack resistance on a semiconductor substrate so as to cover the surface of a stepped pattern. A second silicon oxide film having a superior step coverage is deposited on the first silicon oxide film so as to fill the recessed portions of the stepped pattern and to cover the stepped pattern. The second silicon oxide film is etched to a prescribed thickness. A third silicon oxide film superior in filling of recesses is placed into the recessed portions existing on the surface of the second silicon oxide film after its etching. A fourth silicon oxide film is formed on the semiconductor substrate including the second silicon oxide film and third silicon oxide film.
Abstract: A semiconductor dicing method capable of preventing the silver plating from refusing by heat generated during cutting at thick portions without reducing a large production amount. One end of a semiconductor wafer starts to be cut at a blade feeding speed of 16 mm/sec and the speed is gradually increased. The wafer is cut from a predetermined position to another predetermined position at the constant feeding speed of 40 mm/sec. The speed is then gradually decreased and another end of the semiconductor wafer finishes being cut at the feeding speed of 16 mm/sec. That is, at the cutting start, SPEED UP and at the cutting end, SLOW DOWN. Hence, the thick silver plating are slowly cut and the cutting part is cooled with cooling water. Thus, the heat generated by cutting friction can completely be controlled to prevent the silver plating from refusing.
Abstract: A ring is provided on a monocrystalline silicon wafer at one face thereof and adjacent the edge thereof. The ring increases the optical absorptivity of the wafer adjacent the ring compared to the optical absorptivity of the wafer distant from the ring. The ring therefore at least partially compensates for edge cooling of the wafer during rapid thermal processing thereof. Uniform thickness layers can therefore be deposited on a wafer in a rapid thermal processing system. When depositing polycrystalline silicon on an oxide covered layer, the ring may be formed as a circular trench in the oxide layer adjacent the wafer edge.
Abstract: An encapsulant comprised of alternate layers of polymer and glass gives enhanced protection to semiconductor integrated circuit devices, which is much more effective than either glass or polymer encapsulations by themselves. In one embodiment, a semiconductor device (11) is covered by a polymer layer (13), the polymer layer being covered by a glass layer (14), and the glass layer being covered by a second polymer layer (15). The glass is preferably deposited by a plasma enhanced chemical vapor deposition apparatus (17 of FIG. 2 ).
Abstract: A method of forming a silicon dioxide layer (SiO.sub.2) on a semiconductor substrate which fills gaps between surface features by means of applying, cleaning, and etching a series of layers of silicon dioxide. A layer of SiO.sub.2 is deposited by plasma enhanced chemical vapor deposition of tetraethyl orthosilicate; and a second layer of SiO.sub.2 is deposited thereon by thermal chemical vapor deposition. A series of etches are performed, removing the second layer of SiO.sub.2 from all regions of the substrates except the gaps. A third layer of SiO.sub.2, formed by plasma enhanced chemical vapor deposition, is then deposited. An additional etch step further planarizes the surface of the substrate.
Abstract: A semiconductor processing method of detecting polishing end point from a polishing planarization process includes: a) impinging laser light onto an area of an outermost surface of a semiconductor substrate at an angle of incidence of at least 70.degree. from a line normal relative to the substrate (at least 60.degree. for s-polarized light), the impinged laser light predominantly reflecting off the area as opposed to transmitting therethrough; b) measuring intensity of the light reflected off the area; c) polishing the substrate outermost surface; d) repeating step "a" then step "b"; and e) comparing a prior measured intensity of reflected light with a later measured intensity of reflected light to determine a change in degree of planarity of the semiconductor substrate outermost surface as a result of polishing.
Abstract: The invention relates to the "hardening" (resistance to ionizing radiations) of MOS-type components. In order to avoid the effects of these radiations (creation of electron-hole pairs), there is deposited on a substrate (1) of monocrystalline Si a layer of YSZ (2), and then a thin layer of monocrystalline Si (3). The other steps of production of the components are the same as conventional.
Type:
Grant
Filed:
July 27, 1990
Date of Patent:
March 14, 1995
Assignee:
Thomson-CSF
Inventors:
Louis Mercandalli, Didier Pribat, Bernard Dessertenne, Leonidas Karapiperis, Dominique Dieumegard
Abstract: Synthetic rutile is prepared from titaniferous slags containing alkaline-earth metal impurities, such as magnesium oxide, by a method comprising contacting the slag with chlorine at a temperature of at least about 800.degree. C., and then leaching the chlorine-treated slag with hydrochloric acid at a temperature of at least about 150.degree. C.