Abstract: The present invention is described in several embodiments depicted structures and methods to form these structures. A first embodiment is a structure having a silicon dioxide film bonded to a metal film comprising: a metal nitride film bonded to the metal film; and the silicon dioxide film bonded to the metal nitride film. A second embodiment is a structure having a silicon dioxide film bonded to a metal film comprising: a metal oxide film bonded to the metal film; and the silicon dioxide film bonded to the metal oxide film. A third embodiment is a structure having a silicon dioxide film bonded to a metal film comprising: a metal/oxide/nitride film bonded to the metal film; and the silicon dioxide film bonded to the metal/oxide/nitride film.

Abstract: A thin conformal passivating dielectric film is deposited by ECR-CVD on an IC chip comprising semiconductor devices each of which includes a sub-micron-width irregularly shaped gate electrode. A protective layer of patterned resist is formed overlying each passivated device. Additional dielectric material is then deposited by ECP-CVD, at a temperature below the glass transition temperature of the resist, on the surface of the chip. Subsequently, in a lift-off step, the patterned resist together with the additional dielectric material overlying the resist is removed from the chip.

Abstract: A semiconductor wafer, to form an oxide film, is oxidized in a heat treatment furnace and is annealed if necessary. When said wafer is taken out of said heat treatment furnace, an ambient gas containing water vapor is fed into said heat treatment furnace. The gap linear velocity of the ambient gas is set to 200 cm/min or more. If the ambient gas used at the time when the wafer is taken out of the furnace is a dry gas without water vapor, then an additional heat treatment is carried out using a hydrogen containing atmosphere at low temperature.

Abstract: Disclosed is a method of manufacturing a semiconductor device, comprising the step of forming a dielectric thin film on a semiconductor layer, the dielectric thin film being made of a compound represented by the general formula (1) given below:ABO.sub.3 (1)where "A" is at least one element selected from the group consisting of Ca, Ba, Sr, Pb and La, and "B" is at least one element selected from the group consisting of Zr and Ti,The dielectric thin film being formed by a chemical vapor deposition under a pressure of 400 Torr or less and a temperature of 1,000.degree. C. or less by using a raw material gas containing a complex compound of element A with a .beta.-diketone, a complex compound of element B with a .beta.-diketone, and an oxidizing agent.

Abstract: An improved anneal process is disclosed for use in the preparation of a dielectric layer, especially an intermetal dielectric layer. An oxide layer is deposited using a H.sub.2 O-TEOS PECVD process. A vacuum bake is used to minimize or eliminate volatile water, hydrogen, and hydrocarbon impurities in the dielectric layer. An oxidation anneal is then performed to scavenge any remaining undesirable species, and to provide for densification of the dielectric layer.

Abstract: Tungsten plugs are formed by passivating a substrate having a contact hole with SiH.sub.4, forming a nucleation layer on the passivated substrate by reducing WF.sub.6 with SiH.sub.4 at relatively low pressures and depositing tungsten to substantially fill the contact hole by reducing WF.sub.6 with H.sub.2 at relatively high pressures. Alternatively, rapid thermal annealing is used to cure pinhole defects in a titanium nitride layer on a substrate to avoid the formation of unwanted tungsten volcanoes.

Abstract: A method of forming a dielectric layer on a supporting structure of III-V material having a clean and atomically ordered surface to be coated with a dielectric layer including the step of depositing a layer of Ga.sub.2 O.sub.3, having a sublimation temperature, on the surface of the supporting structure by evaporation using a high purity single crystal of material including Ga.sub.2 O.sub.3 and a second oxide with a melting point greater than 700.degree. C. above the sublimation temperature of the Ga.sub.2 O.sub.3. The evaporation can be performed by any one of thermal evaporation, electron beam evaporation, and laser ablation.

Abstract: The present invention develops an opaque or translucent glass film for use in semiconductor fabrication processes, such as in EPROMs or radio frequency integrated circuits. The opaque or translucent film is developed by forming an glass layer while and introducing a light blocking pigment into the glass layer. The light blocking pigment is made up of a metal oxide, such as titanium oxide (TiO.sub.2), an organic dye, bone ash, or dispersed metal particles. The glass layer is made up of spin on glass.

Abstract: Integrated circuits may be passivated by means of two deposited layers--one of phosphosilicate glass and one of silicon nitride. It was observed that if significant time elapsed between the deposition of the phosphosilicate and the silicon nitride, appreciable degradation of the underlying metallurgy, in the form of voids, occurred. This was traced to a change, over time, in the stresses to which the metallurgy was being subjected--from tensile to compressive. This problem has been solved in the present invention by the provision of a dry environment in which to store the integrated circuits between the application of the two passivation layers.

Abstract: A method for fabricating microelectromechanical systems containing a glass diaphragm formed on a silicon macrostructure is disclosed. The method comprises the steps of: (a) obtaining a silicon wafer and forming a cavity in the silicon wafer; (b) using a flame hydrolysis deposition technique to deposite glass soot into the cavity, the glass soot fills the cavity and extends onto the external surface of the silicon wafer so as to form a glass soot layer having a predetermined thickness; and (c) heat-consolidating the glass soot at temperatures between 850.degree. and 1,350.degree. C. so as to cause the glass soot to shrink and form a glass diaphragm over the cavity. The shrinkage ratio between the glass diaphragm and the glass soot layer is between 1:20 to 1:50. The silicon wafer can be further fabricated to contain a diaphragm-sealed cavity and/or a diaphragm-converted cantilever.

Abstract: A rinse spray bar (24), added to CMP equipment (10), provides complete and uniform wetting and rinsing of the polishing pad (12) for an improved process. The rinse spray bar has a first opening (26) running through a portion of its length and multiple second openings (28) connected to the first opening to create multiple flow paths for a rinse agent. These second openings (28) are capped with spray nozzles (36) on the bottom surface of the rinse spray bar so that the rinse agent can be sprayed out from the second openings at a pressure higher than ambient such that the sprays patterns overlap each other to ensure uniform wetting. An in-line valve (34) adjusts and controls the pressure of the incoming rinse agent through the input line (30) so that the spray nozzle pressure can be varied. The rinse spray bar can be used at every polishing pad station in the CMP apparatus.

Abstract: Methods for measuring the surface area of a top region of a silicon wafer by initially depositing a monolayer of hexamethyldisilizane over the surface area of the silicon wafer. The silicon wafer is then positioned within a vacuum environment. Next, oxygen is introduced into the vacuum chamber so that the HMDS substantially reacts with the oxygen to form products such as carbon dioxide and water. At least one of the water and the carbon dioxide are measured from the known volume of the vacuum chamber. Based on the amount of product formed, the amount of HMDS covering the surface area is determined. Finally, from the amount of HMDS calculated to be originally positioned on the surface area, a value for the surface area is determined.

Abstract: Fabrication of semiconductor devices with movable structures includes local oxidation of a wafer and oxide removal to form a depression in an elevated bonding surface. A second wafer is fusion bonded to the elevated bonding surface and shaped to form a flexible membrane. An alternative fabrication technique forms a spacer having a depression on a first wafer and active regions on a second wafer, and fusion bonds the wafers together with the depression over the active regions. Devices formed are integrable with standard MOS devices and include FETs, capacitors, and sensors with movable membranes. An FET sensor has gate and drain coupled together and a drain-source voltage which depends on the gate's deflection. Selected operating current, channel length, and channel width provide a drain-source voltage linearly related to gate deflection.

Abstract: A BPSG layer serving as a silicon oxide layer is formed on a semiconductor substrate 1. Formed on the surface of the BPSG layer is a hydrophobic molecular layer comprising hydrophobic groups such as methyl, ethyl and the like, by a silylation reaction (in which silyl having hydrophobic groups such as methyl groups, ethyl groups and the like, is reacted with OH groups, and in which the hydrophobic groups are substituted with H of the OH groups to generate --O--Si(CH.sub.3).sub.3 or the like). The molecular layer prevents the BPSG layer from absorbing moisture.

Abstract: A method and structure for sensing data such as temperature with respect to objects such as silicon wafers undergoing fabrication or other processes involve the use of a monitor element of material and configuration similar to that of the objects being processed. A structure such as a closed loop or segment of a spiral may be formed on the surface of the monitor element, and acts as a secondary coil when brought into operative relation with a transformer structure which includes a primary coil, a current source and a sensing device. The sensing device senses variations in the electrical characteristics in the primary coil, caused by the presence of the monitor element, and can thereby determine the temperature or other desired data relating to the monitor element, which is substantially the same as comparable data for the objects being processed.

Abstract: A method depositing a layer onto a wafer is disclosed. The method has the steps of: affixing the wafer to a wafer support within a deposition chamber by using a single-pole electrostatic chuck; depositing a layer onto a surface of the wafer by plasma by CVD; exhausting a deposition gas used for depositing the layer from the deposition chamber; introducing a residual charge removing gas into the deposition chamber; and forming a residual charge removing plasma by discharging the gas to remove residual charges of the single-pole electrostatic chuck.

Abstract: A gas discharge through nitrous oxide or nitrogen is used to remove polymeric deposits that form on the surface of a layer of a spin-on glass that was etched in an atmosphere of carbon-fluorine compounds. Removal of the polymeric deposit greatly improves adhesion to the spin-on glass layer of subsequently deposited layers. The removal is accomplished without increasing any tendency of the spin-on glass layer to absorb moisture.

Abstract: A method of manufacturing a semiconductor device including the steps of: preparing a semiconductor substrate having convexities and concavities on the surface thereof; and generating plasma by using organic silicon having silazane bonding and oxidant and depositing a planarized insulating film on the semiconductor substrate by plasma chemical vapor deposition. The organic silicon may be HMCTSZ and the substrate temperature during deposition is preferably not higher than about 100.degree. C., e.g. 50.degree. C.

Abstract: An improved process to form a planar spin-on-glass layer on a semiconductor body. The process comprises forming a first dielectric layer over a conductive layer. Next, a spin-on-glass (SOG) layer is formed on the first dielectric layer. The SOG layer can be formed of a silicate or a siloxane, each having different process parameters. The SOG solute is dispensed on a stationary wafer. Then two spin cycles are applied to the wafer: a first low speed cycle is applied while the solute is being dispensed on to the wafer and a second high speed cycle. The stationary SOG dispensing and the first low speed cycle allow the solute to more readily fill in tight valleys between metal line. Moreover, the speed and timing of the low speed spin/dispensing allow the proper amount of solvent to evaporate thus increasing the SOG viscosity which improves the planarization for a given thickness of SOG. This process significantly increases the ability of the SOG to fill between closely spaced lines and form a smooth planar layer.

Abstract: An improved method of ozone-TEOS deposition with reduced pattern sensitivity using a two-step low and high temperature process is described. Semiconductor device structures are provided in and on a semiconductor substrate. A conducting layer is deposited overlying the surfaces of the semiconductor device structures and patterned to form conducting lines. An underlayer is deposited overlying the patterned conducting layer. A dielectric layer is deposited in two steps. A first ozone-TEOS layer is deposited over the surfaces of the conducting layer at a first temperature to a first thickness. A second ozone-TEOS layer is deposited over the first ozone-TEOS layer at a second temperature and to a second thickness wherein the second temperature is higher than the first temperature and the second thickness is greater than the first thickness completing the dielectric layer.