Abstract: An electronic calculator system of the type having a keyboard input and a visual display readout is implemented in MOS/LSI semiconductor chips having a data memory, an arithmetic unit, a read-only-memory for storing instruction words, and control circuitry for operating the system in response to keyboard inputs, all in monolithic semiconductor units. The keyboard and display are scanned by timing signals generated in the semiconductor unit by a register associated with the data memory.

Abstract: Interface circuitry for a charged coupled device (CCD) register system. The circuitry enables a PARTIAL-WRITE mode of operation on a CCD storage register. A data bus, which may be bi-directional, is coupled to the sense amplifier of the CCD storage register. The coupling is via interface circuitry responsive to control signals for enabling the register and also enabling a WRITE operation. Discontinuation of the WRITE signals frees the data bus for other uses, thereby allowing for a PARTIAL-WRITE mode of operation. The interface circuitry is simplified so as to require a minimum of space, thereby enhancing the density characteristics of the CCD storage system.

Abstract: A data processing system having a plurality of interrupt sources coupled to provide interrupt handling of a process currently executing at a specified interrupt level. A level change signal which may be generated by the process itself may change the specified level of such process to another level which may make such process less interruptable to other interrupt sources. The level change provided takes place without interrupting the execution of such process.

Abstract: A magnetic tape subsystem includes a peripheral controller which processes data signals of a block received during the reading and recording of the block on a magnetic tape medium by a selected one of a plurality of magnetic tape devices in response to commands received from a data processing system. The peripheral controller includes a data recovery unit having a plurality of storage indicators. These indicators are set by the controller in accordance with the characteristics of the block of data signals recovered by the data recovery unit providing indications of the results of the reading or recording operation performed by the selected magnetic tape device during the peripheral controller's execution of the command. The controller divides up the interval of time of an operation into a number of time periods and monitors the characteristics of the signals of a block which should be received by the data recovery unit during those intervals.

Abstract: A microprogrammed processor which receives 16-bit words as input data from an I/O system, breaks down each received word into four 4-bit bytes, and performs all logical and arithmetic operations on a byte-by-byte basis. The processed bytes may either be stored for further use or reconstituted into 16-bit words and outputted to the I/O system. The processor includes two source buses for applying information to an arithmetic unit (AMU), a destination bus for receiving the AMU output, as well as circuits such as memories and registers for selectively applying AMU input information to the source buses and for receiving AMU output information from the destination bus. Certain ones of the memories can both apply information to source buses and receive information from the destination bus on the same machine operation. Microprogrammed controlled gating facilities specify the circuits that are to be connected to the buses on each machine operation.

Abstract: Apparatus for selecting the operational mode of a particular input/output device in an expandable modular electronic data processing system employing microprocessor devices and testing the I/O device without the use of additional input/output addresses. Input/output interface modules associated with corresponding ones of the I/O devices include a plurality of flip-flops having corresponding memory addresses associated therewith for testing and selecting the operational mode of the I/O device in accordance with the contents of the flip-flops.

Abstract: An automatic scoring system for the game of bowling utilizing 30 scratch memories arranged in 10 successive groups of three, corresponding to the three possible score additions in each of ten successive bowling frames. Input information in the form of successive ball pin scores is sequenced on a common input line to each of the scratch memories. Thirty logic gating circuits, associated with respective individual scratch memories, and operating in time synchronism with the sequenced input information, determine, from the number of ball scores presented and the values of sequential scores, into which one or ones of the scratch memories successive ball scores are entered as a score addition in that place at that time. The system collates consecutive ball scores into the scratch memories such that summation of entries into from one to three of the three scratch memories for a logically determined complete frame represents the score in that frame.

Abstract: A microprogrammed control for a controller operates with an instruction set which includes a pair of microinstructions, each having an op code field. One of the microinstructions has an op code field coded to specify a load constant operation in which a constant field of the microinstruction is loaded into an auxiliary register coupled to the control store of the microprogrammed control. The other microinstruction has an op code field coded to specify an unconditional return branch operation to a location specified by the contents of the auxiliary register loaded previously. Pairs of these microinstructions arranged in a predetermined sequence are included within each routine of microinstructions stored in the control store which the controller is required to execute in parallel.

Abstract: Data transfers between input/output (I/O) devices and a central processing unit (CPU) take place under instruction or base cycle steal control a byte at a time where the I/O device attachments connect to ports and the ports connect to the CPU. Data transfer can be synchronous or asynchronous. The port involved in the data transfer sends out a device address and command information simultaneously on port data bus out and command bus out, respectively, to the I/O attachments. The addressed I/O device can respond any time within a predetermined time interval. If an I/O device does not respond within the time interval, a blast condition generated by the port causes the I/O attachments to clear the busses between it and the port. During execution of an I/O instruction, the CPU clock is first held in a particular time state while phase clocks and port clocks continue to run and synchronization between the port and I/O attachment is taking place.

Abstract: A selection system for an information processing system wherein a unit, such as a magnetic tape unit, is shared by a plurality of control units. At least first and second signal lines are connected between each control unit at a driver circuit and a receiver circuit pair. The two signal lines connected between each control unit correspond to a single shared unit, and each control unit provides a driver circuit and a receiver circuit connected so as to transmit and receive signals carried on each line. Each line is connected to a separate driver circuit and receiver circuit at each control units. A block signal is transmitted from one of the control units through a first signal line to the other control units to prevent them from starting their operation for accessing the shared unit, and selection signals are transmitted from possible plurality of started control units through the second signal line at different timings to thereby determine priority of the started control units for accessing the shared unit.

Abstract: A system for sharing a memory in a fault-tolerant computer. The memory is under the direct control and monitoring of error detecting and error diagnostic units in the fault-tolerant computer. This computer, for example, verifies that data to and from the memory is legally encoded and verifies that words read from the memory at a desired address are, in fact, actually delivered from that desired address. The present invention provides the means for a second processor, which is independent of the direct control and monitoring of the error checking and diagnostic units of the fault-tolerant computer, to share the memory of the fault-tolerant computer and includes circuitry to verify that:1. The processor has properly accessed a desired memory location in the memory;2. A data word read out from the memory is properly coded; and3. No inactive memory was erroneously outputting data onto the shared memory bus.

Abstract: Data storage and processing apparatus for storing and processing data for use by a video display monitor. The data storage and processing apparatus includes a random access memory having a general storage section arranged to store data including display character data to be displayed in horizontal display lines on the display surface of a video display monitor and control data for use in conserving storage space in the random access memory. The memory conservation control data contained in the general storage section of the random access memory includes coded three-character repeat sequences. Each coded repeat sequence specifies a repeat operation and a particular number of times that a display data character is to be repeated in a display line.