Abstract: A data entry system suitable for entry/exit (attendance) recording includes a terminal unit having identity card reading means, adapted to be connected via an extension line to a central apparatus such as a computer controlled telephone line switching system having data handling capabilities. The terminal unit includes a buffer to store the data read from the identity card prior to requesting service from the line switching system and includes a locally generated signal to indicate that the card was correctly read and means responsive to a signal from the central system to indicate that the data was accepted. The card forms a component of the system and is encoded in such fashion that the manner of its use indicates whether entry or exit information is being recorded, and the terminal unit is responsive to the information entered by the card and the response of the central system to provide appropriate logical output at the terminal, such as the activation of an automatic door lock.

Abstract: A train monitoring and reporting system in which each car of a multi-car train is provided with sensors to monitor brake, door, motor and other functions. A controller in each car sequentially and repetitively reviews the condition of each sensed function and evaluates the conditions to determine whether a fault condition exists. The evaluation result is stored and the review is continued and repeated. The lead car of the train repetitively and sequentially interrogates the storage units in each car for each type of fault condition, stores the responses to the interrogation and displays to the motorman any faults reported. The cars communicate through a multiplex data link system which connects the cars in series in a multiplex current loop. The number of times each fault occurs is counted, the count being then available for readout by maintenance personnel.

Abstract: A memory subsystem is connected to an addressable port on one bus and a non-memory subsystem is connected to an addressable port on another bus. Access to the memory is achieved by the non-memory subsystem by generating a message having a destination code indicating an address on its own bus. An inter-bus communication adapter is connected between the buses and intercepts the requesting message. The message is transmitted by the adapter while the destination code is altered to indicate the address of the memory subsystem on the other bus. The receiving memory subsystem responds by generating a response message and placing the source address into the destination address position of the message. The message is transmitted on the bus to which the memory is connected and is intercepted by a second inter-bus communications adapter. The second adapter transmits the response message to the first bus for application to the requesting subsystem.

Abstract: A data processing system in which a programmed supervisor data processing machine and a programmed object data processing machine are interconnected. The object machine is typically a controller which receives input signals from and delivers output signals to interface vector buffer stores under control of an object machine program. The buffer stores connect to and from user devices. The supervisor machine operates to execute a supervisor machine program. The supervisor machine halts and starts the object machine, causes supervisor instructions to be executed in the object machine, extracts information from the object machine and restores the object machine to its prehalt status allowing the object machine to continue processing the object machine program.

Abstract: A transcriber system for the automatic translation of stenographic notes from phonetic outlines produced on a shorthand machine to text displayed or printed out. The basic components of this system are the recording station comprising a shorthand machine, and a tape recorder; and the transcriber station comprising a computer, a disk file, a keyboard-display for editing the original translation into its final form, and an automatic typewriter. The editing process is facilitated by a word cursor which identifies the particular word on display which may be manipulated by the System Editor. However, this cursor also is correlated to the original shorthand machine outlines. Thus, the translation of a term peculiar to the job being processed, or to an individual shorthand machine operator, may be remembered so that subsequent correct translations of these particular outlines will proceed automatically.

Abstract: Memory module construction including separate internal block decoders and system for utilization. Some of the memory modules in a multi-module memory system include a block address decoder providing an external signal when the corresponding module is addressed. A gate, responsive to the external signals, enables the memory modules which do not include a block address decoder. If more than one memory module do not include a block address decoder, then certain address lines or special control lines, in conjunction with the gate, select which memory module is to be enabled.

Abstract: A digital data transfer system having information read-out from a first memory to a user device through temporary storage in an intermediate second memory. The system includes a measuring device which determines the extent to which the second memory is filled with information read-out from the first memory while the information is being transferred to the user device from the second memory. Upon detecting a predetermined first degree of filling, the measuring device produces a first alarm signal which, after a given first delay, is used to temporarily block further read-out of information from the first memory. Afer a predetermined second degree of filling of the second memory in then detected, the measuring device produces a second alarm signal which, after a given second delay, is used to resume the read-out of information from the first memory to the second memory.

Abstract: An arrangement for measuring the load handling capacity of a stored program control process control system. The process control system is first operated in a monitor mode without any load in order to identify the instructions which must be executed independently of load and therefore, may be characterized as "overhead work" instructions. While operating in the no load or monitor mode, each instruction which is executed is flagged by placing "1" in a flag position of the instruction word. The machine includes provisions for executing instructions so flagged with standard machine timing and for executing unflagged instructions with extended machine timing. The unflagged instructions are termed "load related work" instructions and by extending the time required to execute such instructions, the apparent load to the machine is increased, increasing the machine's apparent occupancy. The time for executing a "load related work" instruction is extended by integral numbers of clock frames.

Abstract: Common logic in a peripheral device control unit responds to a serially propagated poll signal from I/O control logic, or channel, along with a coded signal identifying either a poll for a cycle steal request or a poll for an interrupt request having one of several priorities. The poll signal received will be captured or propagated to following control units dependent upon whether the control unit has requested a cycle steal transfer, or has requested an interrupt at the priority level indicated by the coded signal accompanying the poll signal. Proper functioning of poll capture or propagation is possible even though one of the control units is physically removed from the serial chain of control units.

Abstract: The interface between I/O control logic, or channel, and peripheral devices permits simultaneous transfer of command, device address, and data, and includes logic in a peripheral device control unit for dynamic change of the attached peripheral device interrupt priority level while the device may be executing a prior command. The I/O control logic includes means for initiating serial poll signalling while other transfers are taking place on the interface.

Abstract: In order to carry out data transfer among the subsystems of a bus oriented data processing system, each subsystem is coupled to the bus by a local bus adapter which controls both source and destination aspects of the information transfer. Each local bus adapter has a unique "busy" line which may be interrogated by any local bus adapter connected to the bus. When a source subsystem wishes to transfer information to a destination subsystem, the source local bus adapter determines from the destination local bus adapter's busy line whether or not the destination subsystem is available to accept the information. If the destination subsystem is available, the source local bus adapter requests access to the bus from priority resolution apparatus.

Abstract: A data processing machine specifically designed to use a single format of instructions for all operations. The format provides for sufficient information to be provided to enable complex functions to be performed in response to a single instruction. More particularly, a machine organization and an instruction format therefor are disclosed to enable one instruction to enter sufficient control data for control of a long repetitious operation. The instruction is in four sections to enable a function to be specified, to identify one or more operands to be utilized and to specify a number of times the function is to be performed or to specify another limit to the repetitions of the function.

Abstract: A digital processor which is adapted for use in the guidance and stabilization of a guided missile. The digital processor is adapted to store a predetermined macroprogram and to process signals produced by various elements within the missile in accordance with such stored program thereby to produce control signals for the missile's flight control mechanism. A microinstruction memory stores sets of microinstructions, each one of such sets corresponding to one of a number of stored macroinstructions which make up the macroprogram. A register is provided which is adapted selectively to load an addressed microinstruction or a digital test word serially applied by sources external to the missile. In such an arrangement the missile's digital processor may be readily checked out through a relatively simple interface mechanism, also included. In the digital processor is a set of addressable flip/flops adapted to be set or reset by signals both internal to and external to the processor.

Abstract: A data derandomizer for use in a scintillation imaging system. The imaging system produces data signals representing radiation events and presents them to a continuously operating video tape recorder for recording and subsequent playback to an imaging apparatus. The recorder can accept the data signals only in discrete time slots. The digital signals are produced in response to radiation events occurring randomly in time and therefore also occur at random time intervals. A data stacking circuit provides for receipt and simultaneous storage of several data signals between the detector and the recorder, the storage being in priority levels according to the order of occurrence of the data signals. Inventory control circuitry controls the stacking circuit to present the data signals to the recorder synchronously with the time slots, notwithstanding the random occurrence of the data signals.

Abstract: Apparatus for controlling the division of working memory space among n competitive programs with different characteristics, running in a multiprogramming and virtual memory environment, in which the allocation of working space is optimized by adjusting the size of the working set for each competing program. Under this optimization scheme, "the value of a page frame" (the amount of reduction in the page fault rate if an additional page frame is allocated to that program) is sought to be equalized for all programs. Every memory access increments an access counter. When it reaches its maximum count of 1024, the reference register value stored in an associative memory for each page is incremented by one count, except that for the page accessed it is reset to zero. The stored numbers range from 0 to 31. Whenever a page fault occurs, the number of pages of that program having a reference register count equal to each of the numbers 0 to 31 is temporarily stored as a table of 32 Wd values.

Abstract: Data and clock bits are sampled by use of two delay means such as shift registers which are enabled at a clock rate which is set so that a first such delay means coupled to receive the bits includes no more than one bit therein at any time. The receipt of a bit substantially at the midway point of the second delay means, which is coupled serially to receive bits from the first delay means, causes a sampling signal to be generated in response to which a determination is made as to whether another bit has been received by the first delay means. Further logic is provided to recover the data bits.

Abstract: Circuitry external of a microprocessor determines priority between different peripheral devices requesting interrupts to generate a restart vector and a signal granting priority to one of the interrupt-requesting devices. The peripheral device loads its status and address into two addressable registers connected to a common system bus. The restart vector is loaded into the instruction register of the microprocessor. The microprocessor treats the restart vector as an instruction to store the contents of the program counter in memory and loads certain bits of the restart vector into the program counter. These bits represent the starting address of a subroutine of eight instructions for analyzing the interrupt. An interrupt is recognized and the status and identification of the interrupting device is stored in a single instruction cycle. On the next instruction cycle the first instruction of the interrupt analysis routine may begin.

Abstract: A multiprocessor system having a computer poller and a memory poller for controlling information transfer over a time multiplex bus between a plurality of computers and an interleaved memory comprising a plurality of sections. Each poller comprises a counter and a clock so that as the counter is incremented by the clock, each computer or memory section, respectively, is sequentially interrogated to determine whether or not it requires access to a memory or computer, respectively.

Abstract: An information readout apparatus comprises an information memory for successively storing heading information which includes a plurality of heading items and body information associated with said heading information, and wherein the body information is formed of one or more detail information groups, each of which includes a plurality of item numerals. The heading information and body information are distinguished from each other by different positioning codes preceding two forms of information respectively which are detected by a code detector; the heading information read out from the information memory is stored in a buffer memory in response to an output positioning code signal detected by the code detector which represents the heading information; and the heading information is read out from the buffer memory, each time a positioning code associated with the respective detail information groups is read out from the information memory and detected by the code detector.

Abstract: A system for transmitting data which comprises serially arranged records of changeable length. Each record is separated from the adjacent ones by two record positioning codes and includes serially arranged words with word positioning codes interposed among them. If the same item word is included in a record and in the immediately succeeding record, the corresponding word in the succeeding record is omitted or simplified during the data transmission, thereby reducing the memory capacity of the memory for storing the data to be transmitted. Conversely, the system can restore the omitted or simplified item words to the original state and then transmit the data thus in the original state.