Abstract: An input list of N numbers is clocked through a first sort stage having S1 locations entered into an interstage memory as S2 groups of S1 numbers each. The S1 numbers in each group are in numerical order. The first number in each group forms an initial group of S2 numbers which necessarily includes the smallest number of the N input numbers. This initial group is loaded into a second sort stack having S2 locations which arranges the initial S2 numbers in numerical order. The smallest number forms the first number in the output list. A replacement number from the interstage memory is numerically sorted into the second stack each time the smallest remaining number is clocked out. This replacement number is the next number from the same group as the most recently clocked out number. Each new smallest remaining number must either be the second number in the second stack or the replacement number.

Abstract: A circuit for initializing a digital computer. Whenever an operator turns on a power supply for the digital computer or activates a console switch, the circuit transmits overriding address signals. These signals divert the digital computer from a normal initializing routine to a routine provided by the initializing circuit. The routine in the initializing circuit includes digital computer instruction sequences for performing preliminary diagnostic operations and for transferring instructions to a main memory from preselected peripherals. When the routine is complete, the computer is prepared to process other programs and to operate with other peripherals.

Abstract: Circuit arrangement for noncyclic data permutations between the memory cells of a dynamic memory including a permutation network for transferring the contents of a predetermined memory cell into the access port or read-write cell of the memory and an access control system for producing a permutation sequence. The permutation network is comprised of 2.sup.k -1 memory cells which are arranged in a tree-like structure in k of 0 to k-1 numbered planes so that plane i is formed of 2.sup.i memory cells. Each memory cell of plane i is connected to two adjacent interconnected memory cells of plane i+1 so that these three memory cells form a triangle in which the contents of these cells can be cyclically interchanged in a clockwise direction. Each memory cell of the planes 1 .ltoreq. i .ltoreq. k-2 belongs to two triangles while the one memory cell of plane 0, which acts as the access port or read-write cell, and the memory cells of plane k-1 belong to but one triangle.

Abstract: An input list of N numbers is clocked through a first sort stack which provides S2 groups of S1 numbers each arranged in ascending numerical order. The numbers are stored in a buffer where the first location within each group always contains the smallest number in that group. These S2 first numbers are loaded into a second sort stack which arranges them in ascending numerical order. The first location in the second stack contains the smallest number in the entire list of N numbers. This smallest number is clocked out of the second stack to form the first number in the output list. A replacement number is numerically sorted into the second stack from the S2 groups each time the smallest remaining number is clocked out. This replacement number is the next smallest number from the same group as the most recently clocked out number. Each time the smallest remaining number is clocked out, the remaining numbers in the second stack are rearranged to accommodate the replacement number for maintaining numerical order.

Abstract: Input/output registers integrated with logic and arithmetic circuits are combined externally of a processor nucleus having only storage registers, instruction decode logic, timing circuitry and arithmetic and logic unit for executing microinstructions whereby the use of the input/output registers is determined by microprogram code and by time control to either selectively execute all adapter and interface communication and control functions for input and output devices or to selectively be switched into the data flow of the processor nucleus.

Abstract: Apparatus for automatic hyphenation of input words from a word processing system. The apparatus includes a digital reference matrix memory containing a vector representation of all legal hyphenations for each dictionary word in the form of a calculated magnitude and associated unique vector angles. The vector magnitude constitutes the address data for accessing the memory. When an input word is received for hyphenation, a hyphen is added to the word and its magnitude is calculated. The memory is accessed for an address which equals the calculated magnitude. If the address is not found, a signal is generated indicating that the word cannot be legally hyphenated. If the address is found, then the corresponding angles, representing legal hyphenations of the input word, are compared with test words generated by sequentially inserting hyphens in the input word. All equal compares are flagged and the corresponding hyphenated input words are gated onto the output line.

Abstract: In a circuit arrangement composed of highly integrated chips for a microprogrammed data processing device of the type including an arithmetic and control unit, at least one read-only memory, at least one random access memory, connecting contacts on the chips for connection to peripheral units, and a bus connecting the chips together, each contact is connected to a function selecting unit whose operating state is controlled by a microprogram contained in the read-only memory to selectively connect the contact in the arrangement as either an input contact or an output contact. The function selecting unit includes for each contact a bistable circuit and a gating circuit controlled by the microprogram to determine when each contact constitutes an input or an output terminal.

Abstract: A CPU communicates via an indirect memory access channel (IMA) to many devices on a high speed loop and an asynchronous low speed loop. The IMA connects to a loop adaptor (LAD) which connects to the primary parallel loop. A low speed serial loop is coupled to the primary loop through a general device adaptor and another LAD. The time of the loops is broken down into frames divided into inbound and outbound halves. Each half frame carries address and control data. The address in each frame is highly variable depending upon demand by devices and the allocation of service is controlled by interrupt signals by devices on the loops which can demand service whenever an empty or free inbound frame passes by their inputs as indicated by signals known as free bit signals, which are suppressed as soon as a device seizes a free inbound frame.

Abstract: A memory in a device controller divided into sections which are equal in number to the potential number of devices controllable by the controller, each section having a plurality of storage locations for storing the same topology of information in like positioned locations in the other sections is provided, such information including control and status indicators. Apparatus for addressing the locations independent of the addressing of the sections is provided, the sections being addressable independent of the active device or under normal conditions in direct relationship to the identity of the active device so that the information in one section may be changed even though a device associated with another section is then active.

Abstract: A multi-module, multi-port memory system includes modules having semiconductor memory circuits which require periodic refreshing to retain the contents stored therein. Priority circuits resolve conflicts between the multi-port access of the memory modules and the refreshing requirements of semiconductor memory circuits within the modules. The modules of the preferred embodiment are arranged in a polymorphous array of selectably expendable rows and columns. Modules utilizing different memory technologies may be combined within the address space of the array without interfering with independent multi-port access by various computer processors and other memory using devices.

Abstract: A synchronous digital data processing system employing single-phase clock pulses comprises arithmetic and control units which are capable of completing an operation during one clock pulse period. The data processing system includes closed data paths wherein only one stage of a memory circuit capable of the same operation as a master/slave flip-flop is used as a data register in the arithmetic unit and as an address register in the control unit. In either case, during one cycle of a single-phase clock pulse, an input data is set in the memory circuit, and the output of the memory circuit is renewed in response to the input data. The output of the memory circuit is held until it is renewed in the following cycle.

Abstract: Different type devices coupled at random to different channels of a controller therefor, are identified and initial conditions are set by successively comparing known identification codes provided by the controller for known devices with the unknown identification code received from the device whose channel is enabled. In response to positive comparison the identity of the device is known and the controller provides a stored record of such identity and further enables device type specific operations to be provided by the controller.

Abstract: A branch banking system for on-line processing of banking transactions which is responsive to customer-initiated and teller-initiated operations and comprises a plurality of remote branch office terminals and a central controller for establishing transaction validity, maintaining transaction records and customer data. Each branch office terminal includes a branch controller in communication with the central controller and an associated plurality of branch teller stations, each including a teller unit and an associated set of peripheral units. Each teller station includes a teller data display which is responsive to the central controller, by way of its associated branch controller, to display alphanumeric data representative of the transactions.

Abstract: In a computer for executing a program made up of a plurality of instructions stored in an operational memory, in which the system is controlled by a set of microprograms stored in a read-only memory, the program instructions to be executed are transferred one at a time to a scratch pad memory, where they are used to address corresponding microprograms in the read-only memory. The microinstructions of the addressed microprogram are transferred one at a time to a microinstruction register, where each one is used to control the generation of a plurality of sets of commands to various components of the machine for executing the program instruction. The control unit includes means for transmitting control signals and data to the peripheral units with the data being already decoded into a form in which it is able to directly control the data output mechanism of the peripheral unit, without further modifications by a peripheral unit control unit.

Abstract: A serial addressing system for arrays. Each array is comprised of a plurality of charge coupled device (CCD) registers. All of the registers comprising an array are addressed simultaneously, but only one of n arrays is accessed at a time. A serial address forming a stream of up to n bits containing only one 1 bit is propagated through address circuits for n array. The final position of the 1-bit determines which of the n arrays is accessed. Only the address circuits for properly functioning arrays form the bits of an n-bit address shift register, whereas the address circuits for improperly functioning arrays are shorted such that they do not form bits of the n-bit address shift register.

Abstract: A system is provided for coupling an indeterminate number of peripheral devices to a central processing unit (CPU) through a single receptacle. A cable connected to an interface unit (IU) of a first device plugs into the CPU receptacle. Cables of subsequent IUs are plugged into receptacles connected to earlier plugged IUs, thus connecting the cables of all devices in series and the device IU's themselves in parallel. One type of IU is for a magnetic tape cassette and includes a timeout circuit to determine when certain types of programming errors have occurred. A binary digit is set in a status register for that and other types of errors. The status register is read under program control of the CPU, thus providing for the flexibility of haulting operation or bypassing the program section having an error for unattended operation of the CPU.

Abstract: An apparatus for controlling the transmission of multiple level priority interrupt signals to a central processing unit. A number of storage elements are responsive to the interrupt signals on an individual basis. A last-in first-out memory having an output connected to the processing unit stores storing the interrupt signals in order of descending priorities. A comparator circuit compares the priority of a new interrupt signal in the storage element with the highest priority interrupt signal currently in the memory. If the new interrupt signal is of the same or a higher priority, an interrupt request signal is sent to the processing unit. Subsequently, the processing unit returns an acknowledge signal which is operative to load the new interrupt signal into the memory, thereby providing the new interrupt signal as an output therefrom. The acknowledge signal also resets the storage element associated with the new interrupt signal.

Abstract: Ballot receiving, storing, and tallying system, capable of reading individual ballots and of delivering a printed record showing the subtotals of votes cast for the various candidates, propositions, and the like, and incorporating solid-state logic circuits for carrying out various functions of the system. The system includes a digital programmable read-only control memory for storing a group of instruction words representing possible vote marking positions on ballot formats interpreted by the system; a digital ballot image memory for temporarily storing representations of all marks on a ballot sensed as the ballot passes a mark sensing station; and a digital totals memory for maintaining incrementally up-dated totals accumulated for each vote marking position on the ballot. Also included is an interlocking circuit which prevents the accepting and feeding of any ballots, for example, until after a key operated switch has been properly actuated.

Abstract: A key entry and translation system useful with data processing units such as electronic calculators for the purpose of entering desired input information from a keyboard in a predetermined code notation into the data processing units. The present system is of a type wherein the input information from the keyboard is sensed and manipulated in an arithmetic circuit contained within a central processor unit (CPU) in response to program instructions stored in a read-only memory (ROM) and then is entered into the data processing unit through an input buffer contained within a random access memory (RAM). Pursuant to the present system, key entries may be registered during arithmetic operations or printing procedures, through the use of a CPU. Furthermore, the present system is adapted to determine whether the input information from the keyboard is either present or absent before interrogation as to the contents of the input information, for the purpose of speeding up arithmetic operations.

Abstract: In an automatic telephone information retrieval system, each subscriber entry is encoded according to primary name, secondary name, primary address, secondary address, generic occupation and specific occupation. The entire contents of a local telephone directory may be electronically stored at memory addresses based upon the above encoding. Statistical methods are used to ensure a workable distribution of subscriber entries over the available memory addresses. The information is retrieved from memory by successively dividing the memory into "divided down" portions. Division points, which are boundaries between neighboring divisions, are designated in a form directly convertible into address coordinates of a random access core storage to speed information retrieval. Electronic calculating and comparing circuits automatically search the memory as a function of the division points, and also provide rapid and automatic address range computations.