Abstract: In a controller for a host machine such as an electrostatographic copier having a central processing unit module connected via a system bus to an input-output processing unit module, a direct memory access system functioning as part of the input-output processing unit module and operative to provide a high-speed means of refreshing and updating control registers in the host machine by direct accessing of memory in the central processing unit module. The direct memory access system may be programmed to synchronously refresh-update the host machine's control registers as in its normal mode and also asynchronously refresh-update the control registers as in the abnormal mode of a detected electrical disturbance in the electro-sensitive periphery surrounding the control registers, thus requiring restoring thereof.

Abstract: A multipurpose speed controllable processor composed of control memories for storing microprograms, register groups for storing instructions as well as data and the internal states of the processor, all of which serve as parts of the micro instructions, and arithmetic logic units which execute the micro instructions from the microprogram. The arithmetic logic units operate in accordance with operand addresses and codes designated in the micro instructions. Switches are provided for transferring the operand addresses of the micro instructions from the control memories to the register groups, for transferring the operands from the register groups to the arithmetic logic units, for transferring to the register groups the results of the operation of the arithmetic logic units, for transferring the operation codes from the control memories to the arithmetic units and for transferring to a control unit special status information of the operation results in the arithmetic logic units.

Abstract: In a multi-processor system which utilizes store-in-cache techniques, a queueing mechanism for insuring that all units that wish to interrogate a memory line will be permitted to interrogate the line. Backing store access requests for data that is contained in the cache of another processor are queued until they can be serviced. The access requests that pertain to particular data are issued from the queue on a first-in-first-out basis. No group of interrogating units will be able to lock out another unit that wishes to interrogate.

Abstract: A data handling system for a hospital or like establishment. The system keeps track of bed allocation, changes in inventory, and charges to patients, and also serves as a communication network for the hospital. Data is fed into the system in the form of pre-punched cards bearing patient information, inventory data, and commands or messages, and thus unskilled personnel can quickly feed data into the system without error. Message data is routed directly to teleprinters at addressed locations. Bed allocation and patient data, and charge and inventory data are respectively stored in separate magnetic drum storage areas. Searching facilities are provided which can locate desired data entries in either storage area and mark these entries for printout, and separate printout circuitry then transfers marked data items to the proper addresses in the proper format. At the end of each day, a final search is performed which produces a printout of all charges organized by patient number.

Abstract: A data processing system constituted by at least two subsystems, each having at least an integrated combinational logic unit comprising a storage and input/output gates and with which at least two control units are connected. The subsystems are constructed using integrated semiconductor techniques. Peripheral units are connected to the input/output gates. The data path between the control units, among one another or between one control unit and the peripheral units, is routed, respectively, over the storage or over the input/output gates to which the relevant peripheral units are connected. The control unit supplies data signals which cause the aforementioned data path to be completed.

Abstract: Data is transferred between a main memory in a data processing system and communication channels under the control of communications control blocks provided in an auxiliary memory, each of which control blocks includes a starting address, range and status information so as to enable the transfer of data to data blocks included in the main memory as indicated by the starting address in the control blocks. A predetermined number of control blocks is allocated in the auxiliary memory for each communications channel and the transfer of all such data is performed utilizing as many of the predetermined number of control blocks as required for the channel until the transfer is complete as indicated by the last such control block utilized in the transfer. Control blocks are loaded in the auxiliary memory under control of the central processor of the system and are periodically accessed by the processor to determine the status of data transfer operations.

Abstract: A data processing system having a particular configuration of interconnecting data paths among the data handling units thereof. The central processor unit of the system includes a skew-protected quadriport register file having two read and two write input ports as well as a separately located instruction register and a separately located memory address register. The first read port is connected to one of a pair of inputs to an arithmetic-logic unit and the second read port is connected to the other one of the pair of inputs to the arithmetic-logic unit and to the first write port of the register file. The output of the arithmetic-logic unit is connected to the memory address register and to a shifter unit, the shifted output thereupon being connected to the second write port of the register file. The system uses two separate buses for transferring data between the central processor unit and memory units and between the central processor unit and external input/output devices.

Abstract: A controller for directing a host machine which is operative to include a central processor for program execution, a system bus controlled by the central processor for carrying data, address and control signals, and a data memory coupled to the system bus. Additionally included is a direct memory access moudle for conveyance through the system bus of a hold signal to the central processor upon receipt of an enabling signal, and upon acknowledgement for control assumptions of the system bus for generating address and state signals that will directly access the data memory for host machine update.

Abstract: A non-volatile storage module as utilized in a controller for directing a plurality of control registers of a host machine. The controller includes a central processor that is communicatively coupled through a system bus having control data, and address lines to the module and host machine. The non-volatile storage module includes a data memory operative to interface with the system bus for storing data, and for input-output of the data therefrom through the system bus upon command of the central processor. In addition, the module further includes a power storage unit coupled to the data memory for distributing a plurality of power signals from the host machine through a plurality of critical and non-critical power lines to the data memory for providing a power source that may be utilized therein for a power down condition and for sensing a power down condition on the critical power line from the power storage unit for the switching thereof to the data memory.

Abstract: In a control module having a central processor coupled through a system bus including data, address and control lines to access a data memory, a direct access apparatus is included coupled through the system bus to request a hold of the central processor and upon acknowledgement for directly accessing the data memory through the system bus for directing the control registers of a host machine. Also included are a diriment element interfaced to the central processor for receipt of control signals on the system bus from the direct access apparatus for hold request and for transmission of first and second control signals on the system bus from the central processor for acknowledgement, and a timed protocol unit for supervising the data, address and control signals transported on the system bus.

Abstract: A microprocessor has a common data bus coupled to a storage data register, two separate storage address registers and a storage control unit. The data register transfers data to and from a storage unit addressed by that address register selected by a gating means. The address registers can be independently incremented and decremented, and perform either a read or a write operation. All these functions are specified by signals produced from a control word held in the storage control unit.

Abstract: One of a series of hardware/firmware instructions for converting a general purpose digital computer into a database machine by adding the capability of handling data base records. The invention comprises a hardware/firmware implemented machine instruction apparatus which fetches a record descriptor containing a referenced data base record type from main memory. The record type of the record to be checked, which is pointed to by a base register, is also fetched from main memory, and a comparison of the fetched record descriptor and type is made. A condition code is set to indicate the result of the comparison.

Abstract: Computer apparatus which employs a plurality of processing units, a memory unit, and a communication unit, each of the units including a data transfer bus. A bus coupler is provided between each pair of units of differing type to form a distributed data communications network. An addressable, passive task register is associated with one of the units for communication through the couplers and is adapted to register a task priority value associated with a task request, the register being readable by any one of the processor units to obtain the highest priority value registry.

Abstract: Digital data, in the form of serial station bit frames which exclude protocol information, are communicated bidirectionally over a plurality of serial transmission channels to peripheral devices in a digital process control system. Data enters and leaves a process control computer input-output section serially in response to software-generated control signals. Serial-to-parallel station interfaces are located along each channel. Each interface has a multifunctional shift register responding to the control signals to provide not only bidirectional data flow through each station, but simultaneous parallel loading of each peripheral device. One software control logic arrangement eliminates modems and portions of hardwired data flow control logic elements in each station interface, yet operates with a station bit frame which excludes protocol information. Also provided are true interrupt capability at each interface; verification of every bit of input and/or output of each station interface; diagnostics.

Abstract: A data processing system includes a shared functional unit having access and egress through a plurality of communication channels to several data handling units. The communication channels are multiplexed under control of a priority selection circuit normally arranged as a ladder from highest to lowest priority. Request signals for the various channels are each passed through a respective gate conditioned by a request enable device which is susceptible of being disabled whenever a select signal for that particular channel has been caused to serve the associated handling unit while channels of lower priority have request signals still demanding selection. When the request signal of lowest order at the time has been served, all request enable devices are reset in order to return to full priority selection.

Abstract: In a multiprocessor system having a plurality of processors, each of identical construction, each processor is internally equipped with a fixed address supply source which generates a non-unique fixed address for accessing a common memory unit over commonly connected bus lines, and a sequential state indicate signal generator for generating a logic "1" or "0" synchronizing signal when a special condition (for example, interrupt) occurs with respect to the processor.A shared memory access control system for a multiprocessor system, as above described, includes circuitry, external to and associated with at least each processor except for one processor, responsive to the synchronizing signal from its respective processor for modifying the non-unique fixed address from the respective processor so that, as a result, each processor is able to address the common memory over the commonly connected bus lines with a unique fixed address.

Abstract: A relational data base system utilizing magnetic bubble domain storage. The bubble domain storage is located on a magnetic chip and includes storage circuitry for storing bubble domains in columns and rows. The bubble domains are coded to represent data, and the rows and columns of bubbles correspond to tables of data which are determined by various relations. Current activated transfer gates located on the magnetic chip are used to select a particular row or a particular column of bubble domains for accessing. The magnetic chip also includes a write circuit for writing bubble domains into storage and a read circuit for reading bubble domains removed from storage. Located off the magnetic chip are column addressing circuits, row addressing circuits, interface circuitry, and a computer central processing unit.

Abstract: An apparatus matches control code signals and data signals between data processing units which employ different control code formats. The interface is especially suitable for use between a computer bus interface and a controller or between two separate controllers. It employs read-only memory circuits which convert control code signals from the computer bus into discrete controls and commands compatible with the code format of the controller. The read-only memory circuits are programmable to allow looping programs to be implemented.

Abstract: A data processing system using a central processor, in which the free time of the processor is monitored at predetermined intervals. A count is maintained as to the state of the processor at each monitoring, i.e., free or occupied. The chosen interval for monitoring is at least equal to the normal cycle time of the processor between program cycle interrupts. The amount of free time of the computer is determined by this monitoring. The work load or occupancy level of the process is regulated periodically when the free time count is found to be outside of the upper and lower limits which may be revised periodically. This regulation takes the form of limiting or increasing the work input to the system.

Abstract: A typesetting terminal adapted for operating a photo typesetter includes a data processor with a plurality of peripheral devices coupled thereto, such as a keyboard, cathode ray tube display, cursor control and a plurality of tape transports. Information from the keyboard and selected tape transports is read into the data processor memory for access and display by the cathode ray tube and outputting to a further tape device. Desired information can be searched in the various input tapes for display, editing and combination with information derived from another input.