Abstract: The present invention concerns a reverse conduction thyristor. The diode egrated with the thyristor comprises a P + anode, an N layer having slight doping, an N + cathode intended for facilitating the electrical contact and, between the P + cathode and the slightly doped N layer, a thin extra layer of the P type whose presence increases the critical speed of increase of the direct voltage applied to the thyristor in its blocked state.

Abstract: A thyristor is disclosed having a semiconductor body with at least four zones of alternate conductivity type in which the second zone has a control electrode and in which the first zone has a main emitter and first and second auxiliary emitters. The first auxiliary emitter is located between the control electrode and the second auxiliary emitter and the second emitter is located between the first auxiliary emitter and the main emitter. The ratio of the effective edge lengths of the first auxiliary emitter to the second auxiliary emitter and the ratio of the effective edge lengths of the second auxiliary emitter to the main emitter are matched to one another in such a manner that prior to the ignition of the first auxiliary emitter, ignition is initiated on the second auxiliary emitter, and then on the main emitter. The ratio of the effective edge lengths of the first auxiliary emitter to the second auxiliary emitter is .gtoreq.

Abstract: A thermo-ionic diode with a very noise figure, using a special semiconductor structure, is provided. The structure comprises, upon a P.sup.+ doped silicon substrate, a succession of N-doped layers whose thicknesses and impurity ratios are designed to optimize the noise figure, a final P.sup.+ type layer covering the structure. The injecting junction of the diode is located at the transition between the said P.sup.+ layer and the nearest N type layer having a weak doping.

Abstract: A semiconductor controlled rectifier comprising a semiconductor substrate of four-layer structure consisting of alternate P and N layers; a pair of main electrodes kept in ohmic contact with the exposed surfaces of outermost P and N layers; a gate electrode kept in contact with the surface of an intermediate layer; and an auxiliary electrode disposed on the surface of the intermediate layer, which is separated from the gate electrode, lies opposite to the main electrode with respect to the gate electrode, and has a portion located near the main electrode.

Abstract: A dual gate field-effect transistor with two diffusion regions of the same conductivity type and a semi-conductive layer of the opposite conductivity type. Each of the diffusion regions has a second diffusion region thereon of the opposite conductivity type diffused at least partly through the same mask to create narrow, controlled channels but with one of the upper diffused regions extending over the edge of the diffused regions below it. The other upper diffused region has an ohmic contact and serves as a source. Two other ohmic contacts are placed on the metal deposited on thin insulating layers directly over edge parts of the first diffused regions to serve as first and second gate electrodes. Another semi-conductive portion, which may be a diffused region of the other conductivity, has an ohmic contact and serves as a drain.

Abstract: An improved light activated thyristor and a method of fabricating the thyristor are disclosed. The thyristor includes a space charge zone extenable to one end surface of the thyristor body whereby the thyristor may be triggered efficiently with low power light beams. In one embodiment of the device, a notch is formed in an end surface of the thyristor body extending into the space charge region of the forward blocking pn-junction. In another embodiment of the device, a portion of the anodic base region of the thyristor is led up through the cathodic base region to the end surface of the thyristor, whereby the forward blocking junction extends to the end surface of the device.

Abstract: A semiconductor power element comprising two successive opposed polarity planar pn junctions, said element being positively tapered on its lateral surface in the regions of both pn junctions to form an average angle of both tapers of between 30.degree. and 60.degree..

Abstract: The first potential well of a charge-coupled device (CCD) register is initially filled from a source diffusion and then the effective depth of this well is reduced and the excess charge removed. The depth reduction and charge removal may be concurrently accomplished by changing the relative potential between the source diffusion and the electrode or electrodes producing the first potential well in a sense to cause this diffusion to operate as a drain for the excess charge. The charge remaining in the first potential well is relatively noise free, that is, it is at a predictable and reproducible level.

Abstract: A semiconductor component having at least three p-n-junctions which may be switched from a blocking state to a conducting state. The base zone, positioned between the second and third p-n-junctions, is characterized in that it comprises three single zones, the center zone of which is more highly doped and appreciably thinner than either of the two outer zones. The doping concentrations in the two outer zones are equal to one another and appreciably lower than that in a control zone, which is positioned between the first and second p-n-junctions. The effect of the foregoing construction is to reduce the recovery time of the semiconductor component without causing an increase in the forward potential drop, or vice-versa.

Abstract: An electronic thermometer is described that is useful for obtaining oral or rectal body temperatures. The thermometer includes a casing on which is mounted a scale for visually indicating temperature readings. A plug-in connector is used to connect an electrical cord to the casing. Such cord terminates in a disposable semiconductor junction through which a constant current is made to flow so that the voltage developed across it is dependent upon its temperature in a straight line function. The casing encloses small operating batteries and low power consumption circuitry for providing the constant current flow through the semiconductor junction and translating voltage changes developed across it into temperature readings.

Abstract: A junction gated field effect transistor having a substrate providing a drain region of low impurity concentration, a mosaic shaped gate region of high impurity concentration formed on the drain region, a corresponding mosaic shaped insulating layer overlying said mosaic shaped gate region but having windows therein smaller than the windows of the gate region, the windows of the insulating layer being aligned with the windows of the gate region, a gate electrode connected to said mosaic shaped gate region, a plurality of source regions of high impurity concentration formed on the substrate in the openings of the mesh forming the insulating layer, and a conductive plate source electrode overlying said insulating layer and in contact with said source regions.

Abstract: A semiconductor element having a surface coating consisting of, for example, a silicon nitride film and a silicon oxide film covering different surface portions of a semiconductor substrate of, for example, silicon so that such surface coating can be utilized for selective diffusion of impurities such as gallium and antimony. In a semiconductor device thus formed, the surface coating acts as a satisfactory surface protective film against external atmosphere, and the backward characteristics of the PN junction can be improved because the end edge of the PN junction terminating at the substrate surface is covered with the silicon nitride film.

Abstract: A semiconductor device is disclosed which comprises a first region of a first conductivity type, a second region of a second conductivity type and adjacent to said first region, a third region of the first conductivity type and adjacent to fifth regions of the second conductivity type and adjacent to said third region, respectively, and in which said second region is interposed between said first and third regions to isolate them from each other; said third region is interposed between said second, fourth and fifth regions to isolate them from one another; and said first and fifth regions are electrically coupled with each other.

Abstract: A diode-integrated high speed thyristor formed into one body by using a separation region for preventing interference between a thyristor and a diode.

Abstract: Each of at least four electrolytic capacitor packages contains a convolutely wound valve-metal foil capacitor section having package leads connected to tabs that contact the foils in a central region thereof. The package leads extend from one face of each package, and are threaded through holes in a double-sided printed wiring board that serves as a stripline. The anode leads are connected to one metal face of the stripline and the cathode leads to the other, the metal on each face of the stripline covering a major portion of the insulating board. This combination of simple centrally connected foil-type capacitors being connected by means of very short leads to a stripline provides a low impedance multiple capacitor assembly having good high frequency performance and low cost.

Abstract: A multi-channel junction gated field effect transistor which gives good triode characteristics is formed on a substrate of semiconductor material of relatively low impurity concentration of a first conductivity type. A mosaic shape semiconductor gate region of the opposite conductivity type is formed in the substrate below one major surface thereof, the mosaic shape of the gate region forming a plurality of windows filled with portions of the substrate which thus provide channels leading to the main body of the substrate, the main body of the substrate providing the drain region for the transistor. A corresponding relatively thick mosaic shape insulating layer overlies the mosaic shape gate region has a plurality of windows, which windows are smaller than the windows of the gate region and of the same configuration, the windows of the insulating layer being aligned with the windows of the gate region.

Abstract: Power thyristor having rapid triggering, comprising a triggering emitter. the cathode face, the separation line between an intermediate zone of the base and the main emitter, a line from which the firing of the thyristor is effected, has a symmetrical corrugated shape allowing an interdigitation which is also symmetrical. Application to the increasing of the triggering speed of power thyristors without any noticeable reduction in the maximum value of the intensity.

Abstract: A semiconductor switching device is disclosed which has symmetrical operating characteristics in four quadrants, and which is characterized by the substantial elimination of lateral switching currents. In the preferred embodiments, symmetrical semiconductor switching devices are disclosed having five and seven interleaved layers of opposite semiconductor conductivity types. A lower surface of each device is dissected into two areas by a linear groove extending through the outer semiconductor layers to separate apart and electrically isolate one area from the other, while an upper surface is dissected by a groove separating and electrically isolating opposing regions of opposite conductivity types which are formed in the upper surface and which overlap the projected path of the bottom groove.

Abstract: An integrated circuit has semiconductor devices on a substrate. The devices each have gates of polycrystalline silicon and the devices are insulated from each other by a stopper diffused into the substrate between said devices at least in the regions adjacent said gates. Reliability of the integrated circuit is improved by having each polycrystalline silicon gate formed with a region adjacent said stopper diffused with impurity of the same polarity as the impurity diffused in said stopper.

Abstract: A semiconductor material of a first conductivity type has one of its surfaces subjected to high energy oxygen ion implantation, thereby forming an oxide layer below that surface. A gate is formed by masking at least a portion of the surface, exposing the unmasked portion to ion radiation so as to implant impurity ions in the region of the semiconductor material between its unmasked surface and the upper side of the subsurface oxide layer, and metallizing the surface above the implanted region. After removal of the masking material, source and drain areas are formed by high energy ion implantation in the semiconductor material adjacent the lower side of the subsurface oxide layer, the areas having a conductivity opposite the first conductivity type. After windows to the source and drain areas are opened in the semiconductor material and subsurface oxide layer, the exposed surfaces of these areas are metallized.