Abstract: A predistortion circuit for a microwave amplifier and more particularly to predistortion circuit configured as a Doherty amplifier. The predistortion circuit is adapted to be coupled to a downstream Doherty amplifier to precompensate for the gain compression and phase expansion of the downstream Doherty amplifier as the input power level is increased while simultaneously reducing the intermodulation (IM) distortion. In order to provide precompensation, the precompensation circuit is operated at bias level to provide gain expansion and phase compression to cancel out the gain compression and phase expansion of the downstream Doherty amplifier to provide a higher overall linear power added efficiency (PAE).

Abstract: A system and method are provided for controlling the on/off timing relationship between two transistors in a differential that are connected at a tail node to a common current generator. The on/off timing relationship is controlled by on/off signals that control the state of the transistors such that one transistor turns one while the other is turning off. An overlap signal is derived from the tail node excursion and is indicative of whether the on/off signals are overlapping too much or too little. A control signal is generated based on the overlap signal. The timing of driver signals used to derive the on/off signals is adjusted based on the control signal. When more overlap is needed, the timing of the driver signals is adjusted such that there is more overlap of the derived on/off signals. When less overlap is needed, the timing of the driver signals is adjusted such that there is less overlap of the derived on/off signals.

Abstract: Clock information related to a reference clock is distributed from a master network node to a slave network node in an asynchronous packet-based network by embedding the clock information into an additional bit stream and multiplexing the additional bit stream with a primary data stream using an out-of-band channel. Multiplexing the additional bit stream with the primary bit stream using an out-of-band channel may involve selecting yB codes of an xB/yB encoded bit stream to represent bits of the additional bit stream or to balance the running disparity of the xB/yB encoded bit stream. The clock information that is embedded into the additional bit stream is used to generate a clock that is synchronized with a reference clock. In an embodiment, the clock information represents the time difference between a transmitted frame of the additional bit stream and a next edge of the reference clock.

Abstract: System and method for decoding variable-length codes. A variable-length decoder includes an address generator and a local memory unit. The local memory stores a variable-length code look-up table. The local memory can be programmed to include a look-up table supporting substantially any decoding algorithm. In one embodiment, a decoder memory unit and a system memory unit are employed together with the local memory to store a codeword look-up table. The shortest codes are stored in local memory, the next shortest in decoder memory, and the longest codes are stored in system memory. A multistage search algorithm is employed to search for the longest codes. The address generator generates the address of the code table to be searched by adding the value of the bits to be searched to a base address.

Abstract: According to a digital linearizing method, a digital input signal on a first path is operated with an output signal of a main amplifying unit, to thus detect distortion components included in the output signal of the main amplifying unit. A digital input signal on a second path is correlated with the detected distortion components, to thus adaptively control a gain of the digital input signal on the second path during the detection of the distortion components. Therefore, according to the above method, it is possible to effectively and correctly remove the distortion components included in the output signal of the main amplifying unit by amplifying the detected distortion components and coupling the amplified distortion components with the output signal of the main amplifying unit.

Abstract: An analog-to-digital (A/D) converter bank with digital down conversion (DDC) is used to substitute a very-high-speed A/D converter for the UWB transceiver. The A/D converter bank has flexibility and scalability operation functions including the number of low-speed A/D converters, adaptive amplifiers, digital FIR filters or one Mth frequency band digital FIR filter, with operating in parallel, as well as analyzed sequence and synthesized sequence switches. The A/D converter bank for the UWB transceiver has a aliasing free and does not have a phase distortion. The DDC, which has scalability to deal with a multirate operation, is used to shift bandpass signals into baseband signals and decimate the baseband signals according to different down samplings.

Abstract: An apparatus comprising a phase lock loop (PLL) and a lock circuit. The PLL may be configured to multiply an input frequency in response to a lock signal. The lock circuit may be configured to generate the lock signal. The PLL may also be configured to select a reference frequency as (i) the input frequency when in a first mode and (ii) a divided frequency of the input frequency when in a second mode.

Abstract: The present invention provides a serial/parallel A/D converter which is capable of performing a high-speed and high-accuracy operation even in the case where an analog input voltage Vin greatly varies in a period between a previous sampling period in which the analog input voltage is held and the next sampling period, when converting the analog input voltage Vin input into a digital value. This serial/parallel A/D converter includes a lower-order reference voltage initializing circuit 8 for initializing a lower-order reference voltage to an initialization voltage Vrc 23.

Abstract: Device interconnects and methods of making the same are described. In one aspect, a device interconnect system includes a bonding pad portion and a transmission line portion. The bonding pad portion is disposed on a device substrate and is constructed and arranged for electrical connection to a bond wire. The transmission line portion is disposed on the device substrate and is constructed and arranged to electrically couple the bonding pad portion to a device formed on the device substrate. The transmission line portion has a width dimension that is substantially parallel to the device substrate and a height dimension that is substantially perpendicular to the device substrate. The width dimension and the height dimension of the transmission line portion both vary from the bonding pad portion to the device.

Abstract: A concentrated constant type isolator includes an upper member, a lower member, a resin case, a center electrode assembly, a permanent magnet, a resistor element, matching capacitor elements, and a resin member. By setting the electrostatic capacitance value of the matching capacitor element on the input terminal side and that on the output terminal side to appropriate values, the reflection loss characteristic of the concentrated constant type isolator is set such that the center frequency in a pass band is located between the frequency at which the input-side reflection loss becomes a maximum value and the frequency at which the output-side reflection loss becomes a maximum value, and such that the frequency at which insertion loss becomes the minimum value is close to the center frequency, whereby the standard of the insertion loss is satisfied.

Abstract: In a modulator, an attenuator attenuates an input signal, a delay element gives a delay of 1 sample period to the attenuated signal, an adder subtracts a quantized signal that has been fed back with a delay of 1 sample period, from the delayed signal, two or more integrators integrate a result of the subtraction, an adder which adds outputs of the respective integrators and the attenuated signal, and a quantizer quantizes a result of the addition, outputs a result of the quantization as an output signal and feeds back the output signal to the subtractor.

Abstract: A device and associated method for processing a digital information signal from a channel signal. The digital information signal is runlength limited with one or more constraints. The device comprises receiving means for receiving the channel signal and means for comparing a detected runlength with a predetermined value indicative of a minimum runlength constraint or a maximum runlength constraint of the channel signal and for generating a control signal when the detected runlength violates said constraint. The device further comprises substitute means for in response to the control signal deleting or inserting an element in the channel signal.

Abstract: A waveguide is provided on a circuit board thereof with two printed probes that are perpendicular to and spaced from each other by a predetermined distance to receive electric waves guided into the waveguide in two different directions. The two probes are separately located in two rectangular patterns that are provided outside a round pattern. The two rectangular patterns are separately located at a lower or an upper side and to a lateral side of the round pattern and both have a feed opening provided at an edge adjacent to the round pattern. Thus, it is possible to obtain a good cross-polarization isolation between the two probes for them to more effectively receive electric waves without interfering with each other.

Abstract: A buffer circuit and method provide substantially constant output signal edges to facilitate service as a bus driver with enhanced timing flexibility. The buffer circuit includes a NOR gate and a NAND gate for driving output pulldown and pullup transistors. The initiation of current flows through the NOR and NAND gates is controlled by an environmentally adaptive reference circuit. First and second transistors are provided respectively between the NAND gate and the pullup transistor, and between the NOR gate and the pulldown transistor, to produce enhanced sourcing and sinking currents. The enhanced sinking and sourcing currents are timely terminated by switching of the pulldown and pullup transistors to save energy.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: two transistors coupled together in the integrated circuit so that upon the application of complementary voltage signals, electrical charge is substantially evenly distributed between output nodes. Briefly, in accordance with one more embodiment of the invention, an integrated circuit includes: a charge recycle circuit including two transistors. Briefly, in accordance with another embodiment of the invention, an integrated circuit includes: a charge recycle circuit including a first and second transistor coupled so as to respectively receive complementary voltage signals at the control voltage port of the first and second transistors. The transistors have a threshold voltage level different from the threshold voltage level of other transistors coupled to the charge recycle circuit.

Abstract: A field programmable gate array (FPGA) having an array of configuration memory cells arranged in rows and columns. The configuration memory cells store configuration data values for configuring the FPGA. Each configuration memory cell is coupled to a corresponding row line through a corresponding cell access transistor. A row access circuit is coupled to the row lines. To re-program a first set (but not a second set) of configuration memory cells in a column, the row access circuit initially pre-charges each of the row lines, and then provides configuration data values on a first set (but not a second set) of the row lines. All cell access transistors in the column are coupled to a column select line. To avoid losing data in any memory cell, a relatively low read voltage, followed by a higher write voltage, is applied to the column select line. When the read voltage is applied to the column select line, the associated cell access transistors are weakly turned on.

Abstract: A level shift circuit which drops the output voltage of a prior stage circuit to an input voltage level required at a next stage circuit includes a source follower enhancement-type FET, a gate of which is connected as an input terminal, a drain of which is connected to a positive power supply, and a source of which is connected to an anode of a level shift diode; a current adjusting enhancement-type FET, a drain of which is connected to a cathode of the level shift diode, a drain and a gate of which are connected to each other through a constant current source, and a source of which is connected to a negative power supply, an out-put terminal being taken from the connection node of the level shift diode and the constant current source; and a resistor connected between the constant current source and the negative power supply, the current adjusting enhancement-type FET having its gate-to-source voltage controlled by the current flowing through the resistor, thereby adjusting the current flowing through the sou

Abstract: A device and method for data transmission between a transducer and a processing unit which are coupled by one or several signal transmission lines, to selectively activate at least two different modes of operation of the transducer. The device includes a comparator unit which identifies the respectively activated mode of operation by comparing signals present on at least one signal transmission line with predetermined reference signals.

Abstract: Various embodiments of a programmable logic device (PLD) capable of being dynamically partially reconfigured are disclosed. The PLD provides circuitry for changing its configuration data in whole or in part without halting the operation nor losing any of the logic state of the PLD. In one embodiment, data injection circuitry are added to a FIFO architecture to allow the user to inject data at random locations without disturbing the functionality of the PLD. In another embodiment, the PLD architecture is designed to provide for address wide or frame wide accessing of configuration bits. This allows for address wide configuration and reconfiguration.

Abstract: A switchable active termination device internally mounted within a peripheral device and electrically connected to the end of a Small Computer Systems Interface (SCSI) bus cable. Through use of a pair of SCSI active terminator circuit chips, the termination device actively terminates the data lines of the bus cable in a first operating mode in response to a first digital command by providing precise resistive pull-up to a predetermined value on each data line. In a second mode of operation responsive to a second digital command, the termination device disconnects all terminating resistors. Activation of the termination modes is logically driven from an included switch, with visual indication of the presence of an active termination state provided by a light emitting diode.