Abstract: A multiprocessor computer system includes a main memory and a plurality of central processing units (CPU's) which are connected to share main memory via a common bus network. Each CPU has instruction and data cache units, each organized on a page basis for complete operating compatibility with user processes. Each cache unit includes a number of content addressable memories (CAM's) and directly addressable memories (RAM's) organized to combine associative and direct mapping of data or instructions on a page basis. An input CAM in response to a CPU address provides a cache address which includes a page level number for identifying where all of the required information resides in the other memories for processing requests relating to the page. This organization permits the processing of either virtual or physical addresses with improved speed and reduced complexity and the ability to detect and eliminate both consistency and synonym problems.

Abstract: A data transport control apparatus including a storage medium independently accessible by a device interface controller for interconnecting the storage medium and peripherals, a communication bus control for interconnecting the storage medium and a communication bus and a microprocessor bus for interconnecting the storage medium and a microcomputer wherein all interconnections to the storage medium are effectively isolated from each other.

Abstract: An apparatus and a method for interfacing a commercially-available programmable communication interface (PIC) with a magnetic swipe reader or a wand type reader. The invention modifies the raw signals of the magnetic wand and magnetic swipe readers by removing noise and selecting the appropriate reader and track, stretching the clock pulses of the reader, and latching data into a flip-flop until the data is strobed into the PIC.

Abstract: A tag control circuit is provided in a memory access control apparatus of a digital computer system which also includes a central processor having a buffer storage. The tag control circuit includes a tag information store and update circuit and a necessity operation circuit for determining whether invalidation of the tag information and whether transmission of an invalidation information to the central processor are necessary. The tag control circuit also includes a first storage for storing a plurality of access requests of the invalidation operation determined by the necessity operation circuit, a second storage for storing a plurality of invalidation execute information determined by the necessity operation circuit, and a selection circuit receiving a new access request and an access request stored in the first storage and outputting one access request.

Abstract: A data processing system which includes a central processing unit (CPU) to which is connected an I/O bus and a memory bus is disclosed. The data processing system further includes an I/O controller and a video control section. The I/O controller includes a terminal control section which is connected to the CPU through an RS232 Cable, an I/O control section which is connected to the I/O bus over a single line and a single processor for managing both the terminal control section and the I/O control section. The I/O control section includes a plurality of interface and control subsystems each for use with a separate peripheral device and an I/O bus interface and control subsystem. The terminal control section includes a video control section interface through which data is sent directly to the video control section over a separate line, and a keyboard interface for interfacing the terminal control section to a keyboard.

Abstract: A memory system (30) for storing and delivering instructions to a central processing unit (14) in a data processing system includes a main memory (32), a buffer memory (35) and a control unit (42). The main memory includes a series of memory slots (34), each memory slot storing one track. Each track consists of a sequential list of instructions which are executed in order unless a jump instruction is encountered. Each track ends with a jump instruction and begins with an instruction which is a target instruction of at least one jump instruction. The control unit copies each track into the buffer memory prior to delivering instructions from that track to the CPU. This buffer has a pointer (40) which specifies the next instruction in the buffer to be examined. If the instruction is a non-jump instruction, it is delivered to the CPU.

Abstract: In a sequence controller, a sequence program store device includes an instruction store unit for writing a specific instruction dedicated to the sequential control and a plurality of latch circuits respectively associated with the outputs from an output unit. The latch circuits are controlled by a signal from a processing device which periodically calls and processes the program from the store device and executes a specific output processing when external input signals satisfy a logical state set by the program; the latch circuits, if a transition condition of the program is satisfied when the specific instruction is processed, retain an output state of the output unit until the next transition condition is satisfied, and release the state retaining the output state before the next transition condition is satisfied.

Abstract: A sequence control system employing a plurality of programmable logic controllers, each having the same construction and being linkedly connected, can perform complicated sequence control resulting from executing an overall user program based on that of each programmable logic controller while exchanging necessary input/output data; each of the programmable logic controllers can also perform sequence control by itself.

Abstract: To prevent change of data in a non-volatile programmable, ready-only memory (25) forming, together with a microprocessor (23) a control unit, for example for an automotive vehicle, while permitting programming of the memory from an external programming unit (P, 1), an interface (3, 11, 12) is provided through which a release-enable bus (13) also passes, data being transmitted in accordance with a predetermined characteristic--even or odd parity--, the parity correctness being checked. If the parity is correct, an "enter" signal is provided on the release-enable bus for storing the data; if not, retransmission is attempted for a predetermined number of time, and if it cannot be correctly effected, a malfunction indication output signal is generated.

Abstract: A data communication computer network system is arranged to interconnect autonomous computers with a shared single communication channel to provide point-to-point communication between a plurality of computers. Each computer is connected to a channel control means coupled to the shared channel for establishing and removing the point-to-point communication line. Once a point-to-point communication line is established between a source computer and a designated destination computer, all the information, in the form of data packets, to be transmitted therebetween is transmitted without interruption, by means of successive transmission of the data packets.

Abstract: A graphics display apparatus includes a raster-scanned CRT refreshed from a bit-for-pel refresh buffer loaded with bit patterns by a microprocessor corresponding to a desired image. To display shaded areas, additional control logic draws an outline of the area in an auxiliary memory, preferably using Bresenham's Algorithm, according to specified rules. Edge filling logic consisting of EXCLUSIVE-OR gates is used to draw the filled area in the refresh buffer as the outline is read from the auxiliary memory into the refresh buffer. This hardware assistance by the control logic and edge fill logic to the microprocessor enables complex areas to be drawn and filled without unduly degrading the performance of the microprocessor.

Abstract: A word processor includes a keyboard, a cathode-ray tube, a first and a second storage devices, a central processing unit, and an internal storage. The first storage device stores information about the image displayed on the CRT. A floppy disk in which a program for a personal computer is stored can be installed in the second storage device. When the power supply of the word processor is put to work, the CPU ascertains whether such a floppy disk is installed in the second storage device. If installed, the CPU causes the present system to operate as an ordinary word processor. If not installed, the CPU allows the printer to operate in quick response to the input from the keyboard in accordance with the program stored in the ROM of the internal storage device.

Abstract: The topography of a sixteen bit CMOS microprocessor chip including circuitry for enabling it to emulate, under software control, a prior art 6502 microprocessor includes an N-channel minterm logic section including 498 "vertical" diffused minterm lines across which 32 "horizontal" metal lines from an instruction register and a timing generator pass and make selective contact to separate polycrystalline silicon gate electrodes to effectuate a first level of instruction op code decoding. The resulting minterm signals are inverted by a row of CMOS inverters, the outputs of which are connected to polycrystalline lines extending into an N-channel sum-of-minterm section. "Horizontal" metal sum-of-minterm conductors contact various N-channel field effect transistors in the sum-of-minterm region.

Abstract: An electronic translator comprises an input device for entering a first word or words, a first memory circuit for storing the first words, a second memory circuit for storing second words equivalent to the first words, an access circuit for addressing the memory circuits to cause retrieval of the first word or words, or alternately the second word or words, and a control circuit for controlling activation of the access circuit. There may be additionally provided a holding circuit for holding one or more of the first words without translation thereof.

Abstract: In a lock control for a shared storage, each storage controller (SC) includes circuitry (LKA) for holding the addresses locked by any of the storage utilizing units connected thereto and circuitry (FLKA) for holding a copy of the contents of LKAs of the other SCs. When one storage utilizing unit connected to one SC issues a storage access request, its requested address is compared with the contents of the LKA and FLKA in the associated SC, thus determining whether or not the requested address is locked by any other storage utilizing unit connected to that particular SC or by any of the storage utilizing units connected to the other SCs. Each storage utilizing unit may include a FLKA.

Abstract: An electronic postage meter includes two non-volatile memories. One of the non-volatile memories is utilized for storing in historical sequence in respective registers the transaction information for each of a predetermined number of transactions which have occurred prior to the last transaction. This memory is accessed at the time of each transaction. The real-time transaction information may be sequentially written over the earliest information in the registers. The other non-volatile memory stores cumulative data upon power-down.

Abstract: A highspeed, intelligent, distributed control memory system is comprised of an array of modular, cascadable, integrated circuit devices, hereinafter referred to as "memory elements." Each memory element is further comprised of storage means, programmable on board processing ("distributed control") means and means for interfacing with both the host system and the other memory elements in the array utilizing a single shared bus. Each memory element of the array is capable of transferring (reading or writing) data between adjacent memory elements once per clock cycle. In addition, each memory element is capable of broadcasting data to all memory elements of the array once per clock cycle. This ability to asynchronously transfer data between the memory elements at the clock rate, using the distributed control, facilitates unburdening host system hardware and software from tasks more efficiently performed by the distributed control.

Abstract: A translator writing system develops a translator program capable of transforming a user's source code into object code. The language of the source code is summarized in a unique form, namely, a Backus-Nauer Form (BNF). This BNF form of the source code is utilized by the translator writing system to transform the source code into object code. The BNF form takes into account the attribute specifications associated with the language of the source code and the interaction of the attribute specifications in the grammar of the language of the source code. The translator writing system includes a valid testcase generator for testing the developed translator program utilizing every possible correct program statement in the language of the user's source code. The translator writing system further includes an incorrect, invalid testcase generator for testing the developed translator program utilizing every possible incorrect, invalid program statement in the language of the user's source code.

Abstract: A magnetic tape drive emulator provides interface compatibility between a computer system having an industry standard tape drive interface and a peripheral image acquisition processing system. The emulator receives signals that are normally applied to a magnetic tape drive system and converts them into data signals which are formatted for general access by the image acquisition processing system. In addition, the magnetic tape drive emulator converts signals generated by the peripheral processing system into data signals which are formatted for access by the computer system through the standard tape drive interface.

Abstract: In a computer system having a plurality of processors and processes, a semaphore architecture for communication with and between the processes in order to effects coordination and cooperation between processes. The invention is implemented in firmware and software, and divides the work of an entire semaphore operation such that the simple part of the P and V operations (which deliver and pick-up signals to and from the processes, respectively) is done by the firmware; whereas the difficult work of the P or V operation is done by software. Thus the improved architecture increases the speed of the system by the use of firmware and increases the flexibility of the computer system by utilizing software to change functionality.