Abstract: A program scanner for a processor having multiple internal streams of instruction and data flow scans a sequence of incoming codes, and employs a plurality of rams to detect various types of syllables in that code. The contents of these rams are signals indicating the various types of codes possible with the output of the rams then being multiplexed to provide an output indicating which syllables can be grouped together for transmission to various units of the processor.

Abstract: An improved method for communicating updated information among processors in a distributed data processing system. The system includes a plurality of distributed interconnected processors each having a memory. The method includes the steps of prioritizing the processors into a predetermined order, establishing one of the processors as a control processor for the broadcast of update messages, developing an update message in at least one of the processors, selecting in accordance with the control processor one of the processors which has developed an update message as a sender processor, broadcasting the update message of the sender processor to each of the processors, and causing the next processor in order to be selected as control processor in the event that the former control processor fails in service. As one preferred use, the method enables the system to transmit atomic global update messages with a tolerance to multiple processor faults.

Abstract: A memory system connected by means of a system bus to other components of a data processing system. The memory system includes a memory control unit and at least one memory unit in which information units containing two words are stored. The memory control unit is connected to the system bus and receives system addresses and memory commands from the system bus, and depending on the memory command, receives data from or provides data to the system bus. A memory bus and lines for control signals specifying memory requests connect the memory control unit and the memory unit. The memory bus is time multiplexed between memory addresses and information units. The memory control unit receives a memory command, a system address, and in the case of a write command, system data on the system bus and produces the memory requests, memory addresses, and information units required to carry out the memory command.

Abstract: An automatic flight control system having two digital processors receives sensor data over a bit serial data bus through a serial-to-parallel converter. The converter formats the data into bytes corresponding to the data parameters from the sensors. One of the processors controls the bus timing and receives the data bytes which are simultaneously applied to an independent data storage element. An independent address sequencer provides sequential addresses to the independent data storage element at which to store sequential data bytes from the converter. After an entire data frame is stored in the independent data storage element, the second processor performs a bulk move of the data into its local data storage element. The sensors are configured in data subsystems which provide respective messages, each message containing an address identifying the subsystem. These addresses are utilized for directing the data messages to respective areas in the independent data storage element.

Abstract: An input/output (I/O) device controller for a data processing which is implemented on a single printed circuit board, includes a terminal control section, an I/O control section, a processor section and a timing generator section. The terminal control section includes a keyboard interface, an RS232 interface for transmitting and receiving data from the system host CPU over an RS232 line, and a video control section interface. The I/O control section includes a plurality of different I/O interface and control units for connecting the section to a number of different I/O devices and a system I/O bus interface and control unit for interfacing the section to the system I/O bus. The processor section manages the operations of the terminal control section as well as the I/O control section.

Abstract: An ancillary execution unit is interfaced to a primary execution unit of a data processing system where the ancillary unit operates faster than the primary for certain instructions and allows for bypassing the slower unit. The primary execution unit has an instruction input receiving an instruction, an operand input receiving data and an operand output transferring data from the primary execution unit to the data processing system. The ancillary execution unit obtains the instruction from the instruction input, obtains the data from the operand input, performs the function indicated by the instruction to the data, and returns data to the primary execution unit.

Abstract: A word processing system is provided with an interactive display terminal for displaying by character generation a data stream representative of alphanumeric characters to be printed on a document together with means for printing the characters on the document. The processing system integrates into the data stream, data representative of graphics and converts such integrated graphic data into graphic display characters whereby the graphics may also be displayed through character generation. When printing of the graphics and alphanumeric information to produce documents is required, the data in the data stream representative of alphanumeric characters is applied to the printing means resulting in the printing of the characters and the data in the data stream representative of the graphics is applied to apparatus for producing the graphics such as a plotter to produce the graphic content of the document.

Abstract: A system has circuitry for reading out a graphic data string from a source area of a graphic memory, starting from a start address storing the graphic data string, by continuously counting the start address of the graphic memory. The graphic data string read out by this circuitry is stored in a buffer memory. When storage of the graphic data string in the buffer memory is completed, the graphic data string is continuously read out from the buffer memory. The readout graphic data string is written in a destination area, starting from a start address thereof, by continuously counting the start address of the destination area in the graphic memory.

Abstract: When a device on a computer communications bus receives a request to enter into a transaction and is not yet ready to perform the transaction, it sends a retry signal to the requesting device to indicate to it that it should terminate the transaction that it has initiated. If the responding device may later be ready to engage in the transaction if the transaction is initiated again some time in the future, the signal is a retry signal and differs from the signal that the requesting device would receive if the transaction were to be terminated for some other reason. As a result, the master device can be arranged to re-initiate only those transactions for which there is a likelihood that they can be carried out to completion when they are attempted again.

Abstract: In a memory hierarchy system having two or more hierarchy storages of different access speeds and programs and/or data to be loaded on the hierarchy storages, an activity information acquisition unit and a display unit are provided to present information regarding selection of programs and/or data to be loaded on a higher level in memory hierarchy, a unit is provided which automatically decides loading of the programs and/or data on the higher level and executes reallocation of the programs and/or data on the basis of the information, and a unit is provided which permits the user to change the loading by using a user command. The user can make full use of these units during execution of the memory hierarchy control. In an embodiment, priority for the programs and/or data to be loaded on the higher level is calculated and decided. The programs and/or data are written into the real storage in accordance with their priority to increase the real storage hit rate upon occurrence of a next request for loading.

Abstract: In combination with a multiprocessing/multiprogramming computer system having a ring protection mechanism for protecting computer programs from unauthorized access, a new call instruction architecture is implemented partly in firmware and partly in hardware. Also, a new stack mechanism stores hardware managed control information in a control frame and software controlled data in a data frame.

Abstract: The maintenance port system includes a maintenance unit, user prom, an available CRT terminal, and a prom software development package. This system accepts parametric definitions for an automatic panel as defined by the designer, and formats the panel data for display and modification on a CRT (cathode ray tube) terminal. Because the system controls the formats, standard display and modification procedures are then used for transmitting and receiving parameters and are the same from panel to panel.

Abstract: An apparatus for controlling external devices in a controlled installation following a control sequence includes a scanning pulse generator arranged to generate scanning pulses at regularly offset times, and an input detection circuit comprising transition detectors each of which detectors is adapted to accept a distinct input variable signal associated with an external device or system component and a respective one of said scanning pulses to detect a transition or change of state of the input variable signal. An address signal is produced substantially immediately for accessing a sequential memory in response to the presence of a respective one of said scanning pulses and an input transition. The sequential memory stores data identifying the stages in the control sequence wherein the different storage locations are designated by a respective address defined by the particular input channel and a given stage.

Abstract: A list vector control apparatus to be incorporated in a vector processing system includes therein at least a plurality of vector registers. One of the vector registers is operated as a list vector register loading therein list vector elements, while another vector register is operated as a normal vector register to produce list vector data successively with the aid of its address register. The address register is connected to a list vector transfer line for transferring the list vector elements sequentially from the list vector register to produce the desired list vector data.

Abstract: In a multiple-CPU, dynamic path allocation environment. The environment, several devices, such as input/output (I/O) devices, may be accessed through one of a plurality of dynamically configured paths from the CPU. Each path includes a channel, from the CPU, connected to a director. The director, in turn, is connected through respective control module interfaces, to a plurality of control modules, which control modules are used to access a string of devices. The connection method, carried out under control of the director, includes simultaneously polling all of the control modules to determine if any have devices attached thereto that are ready to be connected to the CPU. A response from the control modules, all received simultaneously at the director, identifies the CPU channel through which the connection is to be made. The specific address of the device to be connected is then determined, and the desired connection from the CPU to the device is completed.

Abstract: A unique high-speed hardware arrangement for generating double-level address translations in combination a translation look-aside buffer (TLB) structure that can store and lookup intermediate translations during a double-level translation. The hardware proceeds to the completion of a double-level translation without having to backup its operation, although an intermediate TLB miss is encountered, without danger of CPU deadlock occurring. The hardware arrangement also performs all single-level address translations required by the system.

Abstract: A co-processor is connectable to a main system data bus to run software unknown to the main processor. The main processor can concurrently run other software and maintains priority over shared I/O facilities by providing trapping logic incorporated in a random access memory and dynamically loadable by the master processor which contains data related to the current useability by the co-processor of a shared I/O device. Additional logic is associated with the co-processor to manage interrupts between the co-processor and the system bus.

Abstract: A programmable controller for controlling a plant on the basis of a stored program includes a processing unit for reading out an instruction from a program memory to process the instruction. In the processing unit, it is determined whether the instruction read out from the memory is an instruction taking a register-modified addressing mode or an instruction taking a direct addressing mode. When the read-out instruction is an instruction taking the direct addressing mode, a plant is directly addressed by the address part of the instruction. Then, an arithmetic operation is performed using the state information which is read out from the plant thus addressed, or plant control information is sent from the processing unit to the plant thus addressed.

Abstract: In a programmable controller, addresses for a group of input/output modules are decoded to generate an enable signal to each respective module. To increase the density of I/O circuits per module without increasing the width of the data bus, the I/O modules are provided with enabling circuits that are responsive to a pair of associated enabling signals in one method of I/O scanning and responsive to an enabling signal and two or more byte addresses received in another method of I/O scanning. Circuit paths have been added on a backplane circuit board to allow each enable signal to be coupled to a pair of I/O modules in the first method of I/O scanning. In the second method of I/O scanning, the hardware for carrying out the first method is disabled and byte addresses are used to couple multiple bytes of I/O status to each I/O module.

Abstract: A branch target table (10) is used as an instruction memory which is referenced by the addresses of instructions which are targets of branches. The branch target table consists of a target address table (12), a next fetch address table (14), valid entries table (16) and an instruction table (18). Whenever a branch is taken, some of the bits in the untranslated part of the address of the target instruction, i.e. the instruction being branched to, are used to address a line of the branch target table (10). In parallel with address translation, all entries of the branch target table line are accessed, and the translated address is compared to the target address table (12) entry on that line.