Abstract: A system for determining thickness variation values of a semiconductor substrate comprises a substrate vacuumed to a pedestal that defines a reference plane for measuring the substrate. A measurement probe assembly determines substrate CTV and BTV values, and defines a substrate slope angle. A thermal bonding assembly attaches a die to the substrate at a bonding angle congruent with the substrate slope angle. A plurality of substrates are measured using the same reference plane on the pedestal. Associated methods and processes are disclosed.

Abstract: An object is to provide a semiconductor device that is capable of wireless communication, such as an RFID tag, which can transmit and receive individual information without checking remaining capacity of a battery or changing batteries due to deterioration with time in the battery for a drive power supply voltage, and maintain a favorable a transmission/reception state even when electric power of an electromagnetic wave from a reader/writer is not sufficient. The semiconductor device includes a signal processing circuit, a first antenna circuit connected to the signal processing circuit, an antenna circuit group, a rectifier circuit-group and a battery connected to the signal processing circuit.

Abstract: A method for producing a solar cell having good photoelectric conversion characteristics with high productivity, including the steps of: forming a first electrode on a first main surface of a semiconductor substrate; applying an insulator film precursor to cover at least part of the first electrode; temporarily curing the insulator film precursor; applying a conductive paste to at least the insulator film precursor; curing the conductive paste to form a second electrode; and completely curing the insulator film precursor to form an insulator film, the method in which the step of applying the conductive paste so as to be electrically insulated from the first electrode is performed after the step of temporarily curing the insulator film precursor and at least part of the steps of curing the conductive paste to form the second electrode and completely curing the insulator film precursor to form the insulator film are concurrently performed.

Abstract: The present disclosure generally relates to a method for performing semiconductor device fabrication, and more particularly, to improvements in lithographic overlay techniques. The method for improved overlay includes depositing a material on a substrate, heating a substrate in a chamber using thermal energy, measuring a local stress pattern of each substrate, wherein measuring the local stress pattern measures an amount of change in a depth of the deposited material on the substrate, plotting a plurality of points on a k map to determine a local stress pattern of the substrate, adjusting the thermal energy applied to the points on the k map, determining a sensitivity value for each of the points on the k map, and applying a correction factor to the applied thermal energy to adjust the local stress pattern.

Abstract: A method for forming a mask pattern is provided, comprising forming a negative photoresist on a substrate; in an environment without oxygen, to performing a first exposure on the negative photoresist by use of a first ordinary mask plate, so that a fully-cured portion of the negative photoresist is exposed to light and a semi-cured portion and a removed portion of the negative photoresist are not exposed to light; in an environment with oxygen, performing a second exposure on the negative photoresist by use of a second ordinary mask plate, so that the semi-cured portion of the negative photoresist is exposed to light and the removed portion of the negative photoresist not exposed to light; removing the uncured negative photoresist and forming the mask pattern.

Abstract: Self-aligned isotropic etch processes for via and plug patterning for back end of line (BEOL) interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes removing a sacrificial or permanent placeholder material of a subset of a plurality of holes or trenches through openings in a patterning layer. The method also includes removing the patterning layer and filling the subset of the plurality of holes or trenches with a permanent material.

Abstract: Provided is a light-emitting device that can display an image with a wide color gamut or a novel light-emitting element. The light-emitting device includes a plurality of light-emitting elements each of which includes an EL layer between a pair of electrodes. Light obtained from a first light-emitting element through a first color filter has, on chromaticity coordinates (x, y), a chromaticity x of greater than 0.680 and less than or equal to 0.720 and a chromaticity y of greater than or equal to 0.260 and less than or equal to 0.320. Light obtained from a second light-emitting element through a second color filter has, on chromaticity coordinates (x, y), a chromaticity x of greater than or equal to 0.130 and less than or equal to 0.250 and a chromaticity y of greater than 0.710 and less than or equal to 0.810. Light obtained from a third light-emitting element through a third color filter has, on chromaticity coordinates (x, y), a chromaticity x of greater than or equal to 0.120 and less than or equal to 0.

Abstract: Embodiments relate to fabricating a wafer including a thin, high-quality single crystal GaN layer serving as a template for formation of additional GaN material. A bulk ingot of GaN material is subjected to implantation to form a subsurface cleave region. The implanted bulk material is bonded to a substrate having lattice and/or Coefficient of Thermal Expansion (CTE) properties compatible with GaN. Examples of such substrate materials can include but are not limited to AlN and Mullite. The GaN seed layer is transferred by a controlled cleaving process from the implanted bulk material to the substrate surface. The resulting combination of the substrate and the GaN seed layer, can form a template for subsequent growth of overlying high quality GaN. Growth of high-quality GaN can take place utilizing techniques such as Liquid Phase Epitaxy (LPE) or gas phase epitaxy, e.g., Metallo-Organic Chemical Vapor Deposition (MOCVD) or Hydride Vapor Phase Epitaxy (HVPE).

Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.

Abstract: A display device includes a substrate, a first electrode, an organic light-emitting layer, a second electrode, a phase matching layer, and at least one light-absorbing layer. The substrate includes a plurality of pixel regions and a non-pixel region. The non-pixel region is arranged between adjacent pixel regions. The first electrode is arranged in each pixel region. The organic light-emitting layer is arranged on the first electrode. The second electrode is arranged on the organic light-emitting layer. The phase matching layer is arranged on the second electrode. The at least one light-absorbing layer is arranged on the phase matching layer. A thickness of the second electrode in the non-pixel region is different than a thickness of the second electrode in the pixel regions.

Abstract: Chip package structures and methods for forming the same are provided. The chip package structure includes a first protection layer and a first chip disposed over the first protection layer. The chip package structure further includes a first photosensitive layer surrounding the first chip and covering the first chip and a redistribution layer formed over the first photosensitive layer.

Abstract: A display panel includes a first substrate, an upper capacitor electrode, a capacitor dielectric layer, a second substrate opposite to the first substrate, a conductive bump, an electroluminescent layer, and a counter electrode. The upper capacitor electrode is disposed on an inner surface of the second substrate. The upper capacitor electrode is disposed on an inner surface of the second substrate. The capacitor dielectric layer covers the upper capacitor electrode of the second substrate. The first substrate has at least one pixel electrode and a first capacitor electrode separated from the pixel electrode. The conductive bump is protrusively disposed on the first capacitor electrode of the first substrate. The electroluminescent layer is sandwiched between the pixel electrode and the counter electrode.

Abstract: A semiconductor device has a first interconnect structure formed over the carrier. A semiconductor die is disposed over the first interconnect structure after testing the first interconnect structure to be known good. The semiconductor die in a known good die. A vertical interconnect structure, such as a bump or stud bump, is formed over the first interconnect structure. A discrete semiconductor device is disposed over the first interconnect structure or the second interconnect structure. An encapsulant is deposited over the semiconductor die, first interconnect structure, and vertical interconnect structure. A portion of the encapsulant is removed to expose the vertical interconnect structure. A second interconnect structure is formed over the encapsulant and electrically connected to the vertical interconnect structure. The first interconnect structure or the second interconnect structure includes an insulating layer with an embedded glass cloth, glass cross, filler, or fiber.

Abstract: A method for fabricating a semiconductor device includes forming a gate electrode structure over a first region of a semiconductor substrate, and selectively forming an oxide layer overlying the gate electrode structure by reacting a halide compound with oxygen to increase a height of the gate electrode structure. The halide compound may be silicon tetrachloride, and the oxide layer may be silicon dioxide. The gate electrode structure may be a dummy gate electrode, which is subsequently removed, and replaced with another gate electrode structure.

Abstract: An integrated circuit comprises an inductor over a substrate and a guard ring surrounding the inductor. The guard ring comprises a plurality of first metal lines extending in a first direction and a plurality of second metal lines extending in a second direction. The second metal lines of the plurality of second metal lines are each coupled with at least one first metal line of the plurality of first metal lines. The guard ring also comprises a staggered line comprising a connected subset of at least one first metal line of the plurality of first metal lines and at least one second metal line of the plurality of second metal lines. The first metal lines of the plurality of first metal lines outside of the connected subset, the second metal lines of the plurality of second metal lines outside of the connected subset, and the staggered line surround the inductor.