Abstract: Described are methods for forming multi-component conductive structures for semiconductor devices. The multi-component conductive structures can include a common metal, present in different percentages between the two components of the conductive structures. As described example, multiple components can include multiple ruthenium materials having different percentages of ruthenium. In some applications, at least a portion of one of the ruthenium material components will be sacrificial, and removed in subsequent processing.

Abstract: A flexible packaging architecture is described that is suitable for curved package shapes. In one example a package has a first die, a first mold compound layer over the first die, a wiring layer over the first mold compound layer, a second die over the wiring layer and electrically coupled to the wiring layer, and a second mold compound layer over the second die.

Abstract: A nitride semiconductor device includes a silicon substrate. A nitride semiconductor layer is formed over the silicon substrate. A gate electrode is formed over the nitride semiconductor layer so as to have a first ring-shaped portion and a second ring-shaped portion connected to the first ring-shaped portion. A first finger electrode is surrounded by the first ring-shaped portion. A second finger electrode is surrounded by the second ring-shaped portion. A third finger electrode is interposed between the first ring-shaped portion and the second ring-shaped portion.

Abstract: One or more chips are transferred from one substrate to another by using one or more polymer layers to secure the one or more chips to an intermediate carrier substrate. While secured to the intermediate carrier substrate, the one or more chips may be transported or put through further processing or fabrication steps. To release the one or more chips, the adhesion strength of the one or more polymer layers is gradually reduced to minimize potential damage to the one or more chips.

Abstract: To easily assess a feedback capacitance of a semiconductor element. An assessment method of assessing a feedback capacitance of a semiconductor element is provided, the assessment method including: acquiring a first characteristic correlated with the feedback capacitance and a second characteristic correlated with the feedback capacitance; and assessing the feedback capacitance based on the first characteristic and the second characteristic. The first characteristic may be a characteristic that corresponds to a withstanding voltage of the semiconductor element, and the second characteristic may be an on-resistance of the semiconductor element. In the assessing, the feedback capacitance may be assessed based on a ratio between the first characteristic and the second characteristic.

Abstract: A process of forming a thermal interface material structure includes selectively masking a putty pad that includes ultraviolet (UV) curable cross-linkers to form a masked putty pad. The masked putty pad has a first area that is exposed and a second area that is masked. The process also includes exposing the masked putty pad to UV light to form a selectively cross-linked putty pad. The process includes disposing the selectively cross-linked putty pad between an electrical component and a heat spreader to form an assembly. The process further includes compressing the assembly to form a thermal interface material structure that includes a selectively cross-linked thermal interface material.

Abstract: A semiconductor device may comprise a semiconductor die comprising an active surface and contact pads disposed. Conductive interconnects comprising first ends may be coupled to the contact pads and second ends may be disposed opposite the first ends. An encapsulant may comprise a planar surface disposed over the active surface of the semiconductor die. The planar surface may be offset from the second surface of the conductive interconnects by a distance greater than or equal to 1 micrometer. A build-up interconnect layer may be disposed over the planar surface and extend into the openings to electrically connect with the conductive interconnects. A method of making the semiconductor device may further comprise grinding a surface of the encapsulant to form the planar surface and the conductive residue across the planar surface. The conductive residue may be etched to remove the conductive residue and to reduce a height of the conductive interconnects.

Abstract: Disclosed is a manufacturing apparatus of a light-emitting element including: a main transporting route extending in a first direction, the main transporting route comprising first and second transfer devices connected through a first transporting chamber; a sub-transporting route extending in a second direction intersecting the first direction, the sub-transporting route comprising a second transporting chamber connected to the first or second transfer device and a delivery chamber connected to the second transfer chamber; and a plurality of first treatment chambers connected to the delivery chamber. The main transporting route is configured to transfer a substrate to be treated in a horizontal state, and one of the plurality of treatment chambers is configured to hold the substrate in a vertical state during treatment.

Abstract: Method and system for enhanced charged particle beam processes for carbon removal. With the method and system for enhancing carbon removal, associated method and system for decreasing levels of carbon impurity in depositions, also using a precursor gas in charged particle beam processes (and particularly focused ion beam methodologies), are provided. In a preferred embodiment, the precursor gas comprises methyl nitroacetate. In alternative embodiments, the precursor gas is methyl acetate, ethyl acetate, ethyl nitroacetate, propyl acetate, propyl nitroacetate, nitro ethyl acetate, methyl methoxyacetate, or methoxy acetylchloride.

Abstract: The present disclosure provides a light-emitting device including a substrate, a first block of semiconductor stack on the substrate, a second block of semiconductor stack on the substrate and a third block of semiconductor stack on the substrate. The first block of semiconductor stack includes a first emitting wavelength and a first surface away from the substrate. The second block of semiconductor stack on the substrate includes a second emitting wavelength and a second surface away from the substrate. The third block of semiconductor stack includes s a third emitting wavelength and a third surface away from the substrate. The second surface and the first surface are non-coplanar and the third surface and the first surface are coplanar. The first emitting wavelength, the second emitting wavelength and the third emitting wavelength are different.

Abstract: There is provided a nitride film forming method which includes: performing a pretreatment in which a chlorine-containing gas is supplied while heating a substrate to be processed having a first base film and a second base film formed on the substrate to a predetermined temperature, and is adsorbed onto a surface of the first base film and a surface of the second base film; and forming a nitride film on the first base film and the second base film subjected to the pretreatment, by an ALD method or a CVD method, using a raw material gas and a nitriding gas, while heating the substrate to be processed to a predetermined temperature.

Abstract: A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer. A vertical interconnect structure and semiconductor die are disposed over the first build-up interconnect structure. The semiconductor die, first build-up interconnect structure, and substrate are disposed over a carrier. An encapsulant is deposited over the semiconductor die, first build-up interconnect structure, and substrate. A second build-up interconnect structure is formed over the encapsulant. The second build-up interconnect structure electrically connects to the first build-up interconnect structure through the vertical interconnect structure. The substrate provides structural support and prevents warpage during formation of the first and second build-up interconnect structures. The substrate is removed after forming the second build-up interconnect structure.

Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor substrate, performing an etch process on the semiconductor substrate to form a fin and a trench on opposite sides of the fin, forming an etch guide layer filling the trench, performing an etch process on the etch guide layer to expose a first portion of the fin, and selectively etching the exposed first portion of the fin to remove a portion of the exposed portion of the fin adjacent to an upper first surface of the etch guide layer to form a first nanowire. The method further includes repeating the etch process and the selectively etching process to sequentially form second and third nanowires, and forming a gate structure surrounding the nanowire. The first, second, and third nanowires are formed in the direction perpendicular to the semiconductor substrate.

Abstract: The capacitance between gate structures and source/drain contacts of FinFET devices is reduced by the incorporation of inner spacers in the top portions of the gate structures. A replacement metal gate process used in the fabrication of such devices includes formation of the inner spacers following partial removal of dummy gate material. The remaining dummy gate material is then removed and replaced with gate dielectric and metal gate material.

Abstract: Vacuum annealing-based techniques for forming perovskite materials are provided. In one aspect, a method of forming a perovskite material is provided. The method includes the steps of: depositing a metal halide layer on a sample substrate; and vacuum annealing the metal halide layer and methylammonium halide under conditions sufficient to form methylammonium halide vapor which reacts with the metal halide layer and forms the perovskite material on the sample substrate. A perovskite-based photovoltaic device and method of formation thereof are also provided.

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

Abstract: Subject matter disclosed herein may relate to fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, processes are described, in which an ultraviolet light source is utilized during fabrication of a correlated electron material. In embodiments, use of ultraviolet light may decrease a likelihood of diffusion of atomic and/or molecular components of a substrate that may bring about undesirable electrical performance of a CEM device.

Abstract: A semiconductor memory device includes a semiconductor substrate, transistors formed in an upper surface of the semiconductor substrate, a stacked body provided on the semiconductor substrate, a first contact, and a second contact. The transistors are arranged along a first direction. A minimum period of an arrangement of the transistors is a first period. The stacked body includes electrode films. A configuration of a first portion of the stacked body is a staircase-like having terraces. A first region and a second region are set along the first direction in the first portion. A length in the first direction of the terrace disposed in the second region is longer than the first period. A length in the first direction of the terrace disposed in the first region is shorter than the first period.

Abstract: A light-emitting element is provided. The light-emitting element includes first and second electrodes and an EL layer therebetween. The EL layer includes a light-emitting layer containing first and second substances. The amount of the first substance is larger than that of the second substance. The second substance emits light. Average transition dipole moments of the second substance are divided into three components in x-, y-, and z-directions which are orthogonal to each other. Components parallel to the first or second electrode are assumed to be the components in the x- and y-directions, and a component perpendicular to the first or second electrode is assumed to be the component in the z-direction. The proportion of the component in the z-direction is represented by a, which is less than or equal to 0.2.

Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate, the metal plug is over a silicide layer, and the silicide layer is over a metal oxide layer. The metal oxide layer has an oxygen gradient, such that a percentage of oxygen increases from a top surface of the metal oxide layer to a bottom surface of the metal oxide layer. The metal oxide layer unpins the Fermi level of the interface between the metal plug and the substrate, which is exhibited by a lowered Schottky barrier height (SBH) and increased oxygen vacancy states between the V.B. and the C.B. of the metal oxide layer, which decreases the intrinsic resistivity between the metal plug and the substrate as compared to a semiconductor device that lacks such a metal oxide layer.