Abstract: Disclosed is a display device including a solar cell so as to use power produced by a solar energy, and a method for manufacturing the same, wherein the display device includes light-emitting areas provided on a lower substrate, and a solar cell layer provided on an upper substrate confronting the lower substrate, and provided to produce power by absorbing light, wherein the light-emitting areas include first to third light-emitting areas, and the solar cell layer includes first to third organic solar cell layers which are disposed to areas corresponding to the first to third light-emitting areas.

Abstract: Provided is a semiconductor device having favorable reliability.

Abstract: A semiconductor package includes: a redistribution substrate; a semiconductor chip on the redistribution substrate; and an external terminal on a bottom surface of the redistribution substrate, wherein the redistribution substrate comprises: a first insulating layer including a first opening; a second insulating layer on the first insulating layer and including a second opening, wherein the second opening is positioned in the first opening in a plan view; a first barrier metal layer disposed along a sidewall of the first opening and along a sidewall of the second opening; a first redistribution conductive pattern on the first barrier metal layer; a third insulating layer on a bottom surface of the first insulating layer; and a pad penetrating the third insulating layer and electrically connecting to the first redistribution conductive pattern, wherein the external terminal is provided on the pad, wherein the second insulating layer at least partially covers a chip pad of the semiconductor chip, and the second

Abstract: A storage device including a transistor portion including a transistor, a plurality of interlayer insulating films provided above the transistor portion, a plurality of first conductive layers provided respectively between the plurality of interlayer insulating films, and a second conductive layer extending through the plurality of interlayer insulating films and the plurality of first conductive layers, the second conductive layer having one end electrically connected to the transistor portion, and a part that extends beyond a portion of the transistor portion.

Abstract: A highly reliable light-emitting device and a manufacturing method thereof are provided. A light-emitting element and a terminal electrode are formed over an element formation substrate; a first substrate having an opening is formed over the light-emitting element and the terminal electrode with a bonding layer provided therebetween; an embedded layer is formed in the opening; a transfer substrate is formed over the first substrate and the embedded layer; the element formation substrate is separated; a second substrate is formed under the light-emitting element and the terminal electrode; and the transfer substrate and the embedded layer are removed. In addition, an anisotropic conductive connection layer is formed in the opening, and an electrode is formed over the anisotropic conductive connection layer. The terminal electrode and the electrode are electrically connected to each other through the anisotropic conductive connection layer.

Abstract: A method for increasing the speed of aerosol jet assisted printing a layered perovskite structure comprises applying a PEDOT:PSS layer to a substrate; applying an aerosol mist containing methylammonium iodide and lead iodide, with or without additives, atop the PEDOT:PSS layer with an aerosol jet nozzle; and holding the structure to form a methylammonium lead iodide (CH3NH3PbI3) perovskite thin film layer. The substrate may be an ITO glass or plastic substrate, and the PEDOT:PSS layer may be applied by a process selected from spin-coating, inkjet-printing, slot-die-coating, aerosol jet printing, physical vapor deposition, chemical vapor deposition, and electrochemical deposition. The aerosol mist is generated from a single ink comprising all the constituents of methylammonium lead iodide either dissolved or suspended in one or more compatible solvents or co-solvents. The holding of the CH3NH3PbI3 layer may be performed at about 25-120° C. or lower for 96 hours or less.

Abstract: A scanning antenna is a scanning antenna in which antenna units U are arranged, and includes a TFT substrate including a first dielectric substrate, TFTs, a plurality of gate bus lines, source bus lines, and patch electrodes; a slot substrate including a second dielectric substrate, and a slot electrode formed on a first main surface of the second dielectric substrate; a liquid crystal layer LC provided between the TFT substrate and the slot substrate; and a reflective conductive plate provided opposing a second main surface of the second dielectric substrate opposite to the first main surface via a dielectric layer. The slot electrode includes slots arranged in correspondence with the plurality of patch electrodes, and each of the patch electrodes is connected to a drain of a corresponding TFT and is supplied with a data signal from a corresponding source bus line while selected by a scanning signal supplied from the gate bus line of the corresponding TFT.

Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.

Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.

Abstract: Aspects of the present disclosure provide an integrated circuit (IC) wafer having a plurality of circuit dies each bounded by a set of scribe lines. The IC structure includes: a plurality of reference features each respectively positioned in a first layer of one of the plurality of circuit dies. The reference feature of each circuit die is equidistant from a respective set of scribe lines for the circuit die, and a plurality of identification features each positioned in a second layer of one of the plurality of circuit dies. The reference feature of each circuit die has a distinct offset vector indicative of a positional difference between the identification feature for the circuit die and the reference feature for the circuit die, relative to the identification feature of each other circuit die.

Abstract: An overall displacement tolerance applicable to each pixel tile in a plurality of pixel tiles to be used as parts of an image rendering surface is determined. Each pixel tile in the plurality of pixel tiles comprises a plurality of sub-pixels. Random displacements are generated in each pixel tile in the plurality of pixel tiles based on the overall displacement tolerance. The plurality of image rendering tiles with the random displacements are combined into the image rendering surface.

Abstract: The present disclosure involves forming a porous low-k dielectric structure. A plurality of conductive elements is formed over the substrate. The conductive elements are separated from one another by a plurality of openings. A barrier layer is formed over the conductive elements. The barrier layer is formed to cover sidewalls of the openings. A treatment process is performed to the barrier layer. The barrier layer becomes hydrophilic after the treatment process is performed. A dielectric material is formed over the barrier layer after the treatment process has been performed. The dielectric material fills the openings and contains a plurality of porogens.

Abstract: The present disclosure provides a light-emitting device comprises a substrate with a topmost surface; a first semiconductor stack arranged on the substrate, and comprising a first light-emitting layer separated from the topmost surface by a first distance; a second semiconductor stack arranged on the substrate, and comprising a second light-emitting layer separated from the topmost surface by a second distance; and a third semiconductor stack arranged on the substrate, and comprising third light-emitting layer separated from the topmost surface by a third distance; wherein the first semiconductor stack, the second semiconductor stack, and the third semiconductor stack are configured to emit different color lights; and wherein the second distance is different form the first distance and the third distance.

Abstract: An image sensor includes a two-dimensional array of image sensor pixels, which are formed in a semiconductor layer. Each image sensor pixel is formed in a substrate having a corresponding semiconductor region therein. Each semiconductor region contains at least first and second photoelectric conversion elements, which are disposed at side-by-side locations therein. An electrically insulating isolation region is also provided, which extends at least partially through the semiconductor region and at least partially between the first and second photoelectric conversion elements, which may be configured respectively as first and second semiconductor regions of first conductivity type (e.g., N-type). At least one optically reflective region is also provided, which extends at least partially through the semiconductor region and surrounds at least a portion of at least one of the first and second photoelectric conversion elements. A semiconductor floating diffusion (FD) region (e.g.

Abstract: A semiconductor memory device includes a semiconductor substrate, transistors formed in an upper surface of the semiconductor substrate, a stacked body provided on the semiconductor substrate, a first contact, and a second contact. The transistors are arranged along a first direction. A minimum period of an arrangement of the transistors is a first period. The stacked body includes electrode films. A configuration of a first portion of the stacked body is a staircase-like having terraces. A first region and a second region are set along the first direction in the first portion. A length in the first direction of the terrace disposed in the second region is longer than the first period. A length in the first direction of the terrace disposed in the first region is shorter than the first period.

Abstract: Semiconductor devices and electronics packaging methods include integrated circuit chips having redundant signal bond pads along with signal bond pads connected to the same signal port for non-destructive testing of the integrated circuit chips prior to packaging. Electrical testing is made via the redundant signal bond after which qualified integrated circuit chips can be attached to a pristine and bumped final interposer or printed circuit board to provide increased reliability to the assembled electronic package.

Abstract: A method for forming a pattern includes: forming a preliminary pattern having a plate portion and a plurality of pad portions that protrude from an end of the plate portion over a substrate; forming a first hard mask pattern that includes a blocking portion covering the pad portions and a plurality of line portions partially covering the plate portion; forming a spacer on a sidewall of each of the line portions; forming a second hard mask pattern that fills a space between the line portions by contacting the spacer; forming an opening that exposes the plate portion between the first hard mask pattern and the second hard mask pattern by removing the spacer; and forming a plurality of line pattern portions that are respectively coupled to the pad portions by etching an exposed portion of the plate portion through the opening.

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

Abstract: A significantly reduced parasitic capacitance phase-change material (PCM) radio frequency (RF) switch includes an RF clearance zone including a step-wise structure of intermediate interconnect segments and vias to connect PCM contacts to setback top routing interconnects. The said RF clearance zone does not include cross-over interconnect segments. A low-k dielectric is situated in the RF clearance zone. A closed-air gap is situated in the RF clearance zone within the low-k dielectric. The setback top routing interconnects are situated higher over a substrate than the PCM contacts and the intermediate interconnect segments. The PCM RF switch may further include an open-air gap situated between the setback top routing interconnects.

Abstract: A semiconductor memory device includes a stacked body, a semiconductor portion, a first insulating film, a charge storage layer, and a second insulating film. The stacked body has a plurality of electrode layers stacked in a spaced apart manner from each other. The semiconductor portion is provided in the stacked body and extends in a first direction where the plurality of electrode layers are stacked. The first insulating film is provided between the plurality of electrode layers and the semiconductor portion. The charge storage layer is provided between the plurality of electrode layers and the first insulating film and contains a compound including at least one of hafnium oxide or zirconium oxide and a first material having a valence lower than that of the at least one of the hafnium oxide or the zirconium oxide.