Abstract: A method of forming a semiconductor structure includes providing a stack structure having a first side and a second side opposite the first side. The stack structure includes a bottom wafer comprising a substrate; a plurality of through-silicon vias in the substrate; and a plurality of under bump metallurgies (UBMs) connected to the plurality of through-silicon vias, wherein the UBMs are on the first side of the stack structure. The method further includes attaching a handling wafer on the second side of the stack structure; performing a chip probing process; and removing the handling wafer from the stack structure.

Abstract: A system and method is disclosed for manufacturing a bipolar junction transistor that comprises an emitter/base layer that is formed by a single deposition process. In one advantageous embodiment of the invention the emitter/base layer comprises an emitter layer that comprises an epitaxially grown mono-silicon emitter. The epitaxially grown mono-silicon emitter significantly reduces the electrical resistivity of the emitter. A non-dopant impurity such as germanium is added to the base layer to endpoint a dry plasma etch process that is applied to etch the emitter/base layer.

Abstract: A chip package includes a thermal interface material disposed between a die backside and a heat sink. The thermal interface material includes a first metal particle that is covered by a dielectric film. The dielectric film is selected from an inorganic compound of the first metal or an inorganic compound coating of a second metal. The dielectric film diminishes overall heat transfer from the first metal particle in the thermal interface material by a small fraction of total possible heat transfer without the dielectric film. A method of operating the chip includes biasing the chip with the dielectric film in place.

Abstract: A method of manufacturing a thin film transistor array panel, including: forming gate lines on a substrate; forming a gate insulating layer on the gate lines; forming semiconductor layers on the gate insulating layer; forming data lines and drain electrodes on the semiconductor layers; depositing a passivation layer on the data lines and the drain electrodes; forming a first photoresist layer including a first portion and a second portion that is thinner than the first portion on the passivation layer; forming a first preliminary contact hole exposing the data lines by etching the passivation layer by using the first photoresist layer as a mask; removing the second portion of the first photoresist; forming a first contact hole by expanding the first preliminary contact hole and opening portions by etching the passivation layer by using the first portion of the first photoresist layer as a mask; depositing a conductor layer; and forming pixel electrodes in the opening portions and a first contact assistant mem

Abstract: Measurement of the extinction coefficient k is employed for effective and prompt in-line monitoring and/or controlling of the metal film composition. The dependency of the extinction coefficient on the composition of a metal compound is characterized by measuring the extinction coefficients of a series of the metal compound with different compositions. A monitor metal film is then deposited on a wafer. The extinction coefficient k of the film on the wafer is measured and a film compositional parameter is extracted. The wafer processing may continue if k is in specification or the needed compositional change in the film may be extracted from the measured value of the k and the established dependence of k on the composition of the film for out-of-spec k values.

Abstract: A method for manufacturing an organic light emitting diode includes a lower substrate, a luminous element provided with upper and lower electrodes, and disposed on the lower substrate, a shielding layer disposed on the luminous element for shielding outer moisture, the shielding layer being formed of at least one layer, and an upper substrate disposed on the shielding layer.

Abstract: The invention includes methods in which an angled implant is utilized to self-align a source/drain region implant with the top edge of a gateline of a vertical transistor structure. The invention also includes methods in which an angled implant is utilized to implant dopant beneath the gateline of a vertical transistor structure. Vertical transistor structures formed in accordance with methodology of the present invention can be incorporated into various types of integrated circuitry, including, for example, DRAM arrays.

Abstract: A method for manufacturing a semiconductor device of the present invention is provided including the steps of forming a first conductive layer over a substrate; forming a second conductive layer containing a conductive particle and resin over the first conductive layer; and increasing an area where the first conductive layer and the second conductive layer are in contact with each other by irradiating the second conductive layer with a laser beam. By including the step of laser beam irradiation, the portion where the first conductive layer and the second conductive layer are in contact with each other can be increased and defective electrical connection between the first conductive layer and the second conductive layer can be improved.

Abstract: Methods of manufacturing a semiconductor device include forming a matrix of active pillars including a channel part on a substrate. Channel dopant regions are formed in the channel parts of the active pillars. Gate electrodes are formed on an outer surface of the channel parts that surround the channel dopant regions. The matrix of active pillars may be arranged in rows in a first direction and in columns in a second direction crossing the first direction on the substrate.

Abstract: In a flip chip mounted body in which a semiconductor chip (20) having a plurality of electrode terminals (21) is disposed so as to be opposed to a wiring board (10) having a plurality of connection terminals (11), with the connection terminals (11) and the electrode terminals (21) being connected electrically, a resin (13) containing electrically conductive particles (12) is supplied between the connection terminals (11) and the electrode terminals (21), the electrically conductive particles (12) and the resin (13) are heated and melted, and vibrations are applied so as to make them flow. The molten electrically conductive particles (12) are allowed to self-assemble between the connection terminals (11) and the electrode terminals (21), thereby forming connectors (22) that connect them electrically.

Abstract: A semiconductor structure. The semiconductor structure includes: a substrate having a metal wiring level within the substrate; a capping layer on and above a top surface of the substrate; an insulative layer on and above a top surface of the capping layer; an inductor comprising a first portion in and above the insulative layer and a second portion only above the insulative layer; and a wire bond pad within the insulative layer, wherein the first portion the inductor has a height in a first direction greater than a height of the wire bond pad in the first direction, wherein the first direction is perpendicularly directed from the top surface of substrate toward the insulative layer.

Abstract: The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises defining a photoresist feature having a first size in a layer of photoresist that is formed above a layer of dielectric material. The method further comprises reducing the first size of the photoresist feature to produce a reduced size photoresist feature, forming an opening in the layer of dielectric material under the reduced size photoresist feature, and forming a conductive material in the opening in the layer of dielectric material.

Abstract: A method of fabricating a semiconductor device is provided. Spacers can be formed on adjacent gate structures and used as an ion implantation mask for forming source/drain regions. The spacers can include a nitride layer and an oxide layer. An etch stop layer can be provided between the gate structures, and the oxide layer can be removed from the spacers. A first oxide layer formed below the nitride layer can be protected from being etched away during removal of the oxide layer from the spacers by the etch stop layer. The etch stop layer and the first oxide layer can be removed, and an interlayer dielectric layer can be deposited.

Abstract: A method of a semiconductor device. A substrate is provided. At least one metal wiring level is within the substrate. An insulative layer is deposited on a surface of the substrate. An inductor is formed within the insulative layer using a patterned plate process. A wire bond pad is formed within the insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor.

Abstract: A method of forming a semiconductor substrate. A substrate is provided. At least one metal wiring level is within the substrate. A first insulative layer is deposited on a surface of the substrate. A portion of a wire bond pad is formed within the first insulative layer. A second insulative layer is deposited on the first insulative layer. An inductor is within the second insulative layer using a patterned plate process. A remaining portion of the wire bond pad is formed within the second insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor.

Abstract: A semiconductor device is formed using a semiconductor substrate. A gate dielectric is formed over the semiconductor substrate. A gate electrode layer is formed over the gate dielectric. A patterned masking layer is formed over the gate electrode layer. A first region of the gate electrode layer lies within an opening in the patterned masking layer. The first region of the gate electrode layer is partially etched to leave an elevated portion of the gate electrode layer and a lower portion adjacent to the elevated portion. A sidewall spacer is formed adjacent to the elevated portion and over the lower portion. An implant is performed into the semiconductor substrate using the elevated portion and the sidewall spacer as a mask. The sidewall spacer and the lower portion are removed.

Abstract: A method of forming a metal wiring includes: forming a foundation layer on a substrate; applying a solution including fine metal particles and a dispersion stabilizer on the foundation layer; and heating the applied solution to form into a conductive layer, wherein after the applying of the solution, the conductive layer is formed by starting the heating of the applied solution within a detained time.

Abstract: A method of forming a field effect transistor comprises providing a substrate comprising a biaxially strained layer of a semiconductor material. A gate electrode is formed on the biaxially strained layer of semiconductor material. A raised source region and a raised drain region are formed adjacent the gate electrode. Ions of a dopant material are implanted into the raised source region and the raised drain region to form an extended source region and an extended drain region. Moreover, in methods of forming a field effect transistor according to embodiments of the present invention, a gate electrode can be formed in a recess of a layer of semiconductor material. Thus, a field effect transistor wherein a source side channel contact region and a drain side channel contact region located adjacent a channel region are subject to biaxial strain can be obtained.

Abstract: A separation layer is formed over a substrate having a depressed portion, using a silane coupling agent; a conductive layer and an insulating layer that covers the conductive layer are formed in the depressed portion over the separation layer; and a sticky member is attached to the insulating layer, then the conductive layer and the insulating layer are separated from the substrate. Alternatively, after these steps, a flexible substrate is attached to the conductive layer and the insulating layer.

Abstract: A method of forming a pattern having a step difference and a method of making a thin film transistor and an LCD device using the method of forming the pattern. The method of forming a pattern having a step difference includes forming a first pattern having a predetermined shape in a first printing roll, rotating the first printing roll on a substrate to transfer the first pattern onto the substrate, forming a second pattern having a predetermined shape in a second printing roll, and rotating the second printing roll on the substrate onto which the first pattern is transferred, to transfer the second pattern onto the substrate.