Patents Examined by Michael Trinh
  • Expitaxial fabrication of fins for FinFET devices
    Patent number: 8017463
    Abstract: A fin for a finFET is described. The fin is a portion of a layer of material, where, another portion of the layer of material resides on a sidewall.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: September 13, 2011
    Assignee: Intel Corporation
    Inventor: Peter L. D. Chang
  • Semiconductor architecture having field-effect transistors especially suitable for analog applications
    Patent number: 8013390
    Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) has a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108 or 268). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material preferably includes a more heavily doped pocket portion (120 or 280) situated along the other source/drain zone (102 or 262).
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: September 6, 2011
    Assignee: National Semiconductor Corporation
    Inventor: Constantin Bulucea
  • Method of manufacturing semiconductor device
    Patent number: 8008190
    Abstract: Disclosed is a method of manufacturing a semiconductor device which includes: providing an insulating film formed above a semiconductor substrate with a processed portion; supplying a surface of the processed portion of the insulating film with a primary reactant from a reaction of a raw material including at least a Si-containing compound; and subjecting the primary reactant to dehydration condensation to form a silicon oxide film on the surface of the processed portion.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: August 30, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuhide Yamada, Hideto Matsuyama, Hideshi Miyajima
  • Semiconductor device fabricating method and fabricating apparatus
    Patent number: 8003437
    Abstract: Respective attracting openings of a bonding head are disposed so as to avoid joining regions at which bump electrodes (obverse electrodes) of a semiconductor chip are joined with bump electrodes of a package substrate. Bump electrodes (reverse electrodes) that are connected to the bump electrodes are provided at a reverse side of the semiconductor chip at positions opposing the bump electrodes. Because the attracting openings do not overlap the joining regions, the bump electrodes (reverse electrodes) are not suctioned at the joining regions.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: August 23, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Yoshihiro Saeki
  • Method for dehydrogenation treatment and method for forming crystalline silicon film
    Patent number: 7998841
    Abstract: A dehydrogenation treatment method which includes forming a hydrogenated amorphous silicon film above a non-heat-resistant substrate, and eliminating bonded hydrogen from the hydrogenated amorphous silicon film by irradiating an atmospheric thermal plasma discharge to the hydrogenated amorphous silicon film for a time period of 1 to 500 ms. The surface of the substrate is heated at a temperature of 1000 to 2000° C. by irradiating the atmospheric thermal plasma discharge.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: August 16, 2011
    Assignee: Advanced LCD Technologies Development Center Co., Ltd.
    Inventors: Kazufumi Azuma, Hajime Shirai
  • Method for manufacturing CIS-based thin film solar cell
    Patent number: 7989256
    Abstract: In order to manufacture a CIS-based thin film solar cell that can achieve high photoelectric conversion efficiency by adding an alkali element to a light absorbing layer easily and with good controllability, a backside electrode layer (2) is formed on a substrate (1). Then, a p-type CIS-based light absorbing layer (3) is formed on backside electrode layer (2), and then an n-type transparent and electroconductive film (5) is formed on this p-type CIS-based light absorbing layer (3). At this time, the backside electrode layer (2) is constituted by forming a first electrode layer (21) using a backside electrode material in which an alkali metal is mixed and, then forming a second electrode layer (22) using the backside electrode material that does not substantially contain the alkali metal.
    Type: Grant
    Filed: May 18, 2009
    Date of Patent: August 2, 2011
    Assignee: Showa Shell Sekiyu K.K.
    Inventors: Hideki Hakuma, Yoshiaki Tanaka, Satoru Kuriyagawa
  • Light emitting diode and fabrication method thereof
    Patent number: 7989235
    Abstract: A light emitting diode (LED) and a method for fabricating the same, capable of improving brightness by forming a InGaN layer having a low concentration of indium, and whose lattice constant is similar to that of an active layer of the LED, is provided. The LED includes: a buffer layer disposed on a sapphire substrate; a GaN layer disposed on the buffer layer; a doped GaN layer disposed on the GaN layer; a GaN layer having indium disposed on the GaN layer; an active layer disposed on the GaN layer having indium; and a P-type GaN disposed on the active layer. Here, an empirical formula of the GaN layer having indium is given by In(x)Ga(1-x)N and a range of x is given by 0<x<2, and a thickness of the GaN layer having indium is 50-200 ?.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: August 2, 2011
    Assignee: LG Innotek Co., Ltd
    Inventor: Seong Jae Kim
  • Semiconductor device with strained transistors and its manufacture
    Patent number: 7985641
    Abstract: A semiconductor device has: a semiconductor substrate made of a first semiconductor material; an n-channel field effect transistor formed in the semiconductor substrate and having n-type source/drain regions made of a second semiconductor material different from the first semiconductor material; and a p-channel field effect transistor formed in the semiconductor substrate and having p-type source/drain regions made of a third semiconductor material different from the first semiconductor material, wherein the second and third semiconductor materials are different materials. The semiconductor device having n- and p-channel transistors has improved performance by utilizing stress.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: July 26, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Young Suk Kim, Yosuke Shimamune
  • System and method for faceting the corners of a resistor protect layer to reduce vertical step height
    Patent number: 7982287
    Abstract: A system and method is disclosed for providing a resistor protect layer to protect a thin film resistor in a semiconductor device. A thin film resistor is formed on a dielectric layer and a resistor protect layer is placed over the thin film resistor. An etch procedure is employed to facet the corners of the resistor protect layer. The faceted corners of the resistor protect layer reduce the step height of the resistor protect layer. Then a conductor is deposited over the resistor protect layer and the dielectric layer. When portions of the conductor are subsequently etched away, the resistor protect layer protects the underlying thin film resistor from being exposed to the etch process.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: July 19, 2011
    Assignee: National Semiconductor Corporation
    Inventor: Rodney Hill
  • Semiconductor device and method of manufacturing the same
    Patent number: 7977189
    Abstract: The present invention relates to a semiconductor device that includes a semiconductor substrate (10) having source/drain diffusion regions (14) formed therein and control gates (20) formed thereon, with grooves (18) being formed on the surface of the semiconductor substrate (10) and being located below the control gates (20) and between the source/drain diffusion regions (14). The grooves (18) are separated from the source/drain diffusion regions (14), thereby increasing the effective channel length to maintain a constant channel length for charge accumulation while enabling the manufacture of smaller memory cells. The present invention also provides a method of manufacturing the semiconductor device.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: July 12, 2011
    Assignee: Spansion LLC
    Inventor: Masahiko Higashi
  • Method of crystallizing silicon
    Patent number: 7977217
    Abstract: A method of crystallizing silicon including preparing a substrate having an amorphous silicon film formed thereon, aligning a mask having a first energy region and a second energy region over a first region of the amorphous silicon film formed on the substrate, irradiating a laser beam through the first and second energy regions of the mask onto the first region of the amorphous silicon film, crystallizing the first region of the amorphous silicon film by irradiating the laser beam through the first energy region of the mask, and activating the crystallized first region by irradiating the laser beam through the second energy region.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: July 12, 2011
    Assignee: LG Display Co., Ltd.
    Inventor: JaeSung You
  • Method of fabricating semiconductor device
    Patent number: 7972912
    Abstract: A method of fabricating a semiconductor device includes first providing an insulation substrate. A patterned conductive layer is formed over the insulation substrate, and the patterned conductive layer includes a channel region and a number of protruding regions. A gate structure layer is formed over the insulation substrate. The gate structure layer covers a part of the patterned conductive layer, and each of the protruding regions has an exposed region. A doping process is performed to dope at least the exposed region of the patterned conductive layer to form a number of S/D regions.
    Type: Grant
    Filed: January 13, 2009
    Date of Patent: July 5, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Huai-Yuan Tseng, Chen-Pang Kung, Horng-Chih Lin, Ming-Hsien Lee
  • III-nitride semiconductor device
    Patent number: 7973304
    Abstract: A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof.
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: July 5, 2011
    Assignee: International Rectifier Corporation
    Inventors: Robert Beach, Zhi He, Jianjun Cao
  • Method for forming trench isolation using a gas cluster ion beam growth process
    Patent number: 7968422
    Abstract: A method of forming shallow trench isolation on a substrate using a gas cluster ion beam (GCIB) is described. The method comprises generating a GCIB, and irradiating the substrate with the GCIB to form a shallow trench isolation structure by growing a dielectric layer in at least one region on the substrate.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: June 28, 2011
    Assignee: TEL Epion Inc.
    Inventor: John J. Hautala
  • Nonvolatile memory devices and methods of fabricating the same
    Patent number: 7955869
    Abstract: Nonvolatile memory devices and methods of fabricating the same are provided. In some embodiments, a nonvolatile memory device includes a lower conductive member formed on an upper part of or inside a substrate, a ferroelectric organic layer formed on the lower conductive member, a protective layer formed on the ferroelectric organic layer, and an upper conductive member formed on the protective layer to cross the lower conductive member.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: June 7, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yasue Takahiro, Byeong-Ok Cho, Moon-Sook Lee
  • Semiconductor device having a field effect transistor using a high dielectric constant gate insulating film and manufacturing method of the same
    Patent number: 7956413
    Abstract: In a method for manufacturing a semiconductor device having an N-channel field effect transistor, the N-channel field effect transistor is formed by a process including the steps of forming a high dielectric constant gate insulating film on a substrate, forming a gate electrode on the high dielectric constant gate insulating film, forming an extension region by introducing N-type impurities into the substrate by using at least the gate electrode as a mask, and forming a pocket region by introducing P-type impurities under the extension region in the substrate by using at least the gate electrode as a mask. An amount of arsenic (As) that is introduced as the N-type impurities is in a range that is equal to or lower than a prescribed value that is determined based on a thickness of the high dielectric constant gate insulating film.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: June 7, 2011
    Assignee: Panasonic Corporation
    Inventors: Yoshinao Harada, Shigenori Hayashi, Masaaki Niwa
  • Semiconductor device manufacturing method
    Patent number: 7955970
    Abstract: A process for producing a semiconductor device, comprising the wiring region forming step of forming a wiring region on a semiconductor substrate; the copper wiring layer forming step of forming a copper wiring layer on the formed wiring region by electrolytic plating technique, wherein the copper wiring layer is formed by passing a current of application pattern determined from the relationship between application pattern of current passed at electrolytic plating and impurity content characteristic in the formed copper wiring layer so that the impurity content in the formed copper wiring layer becomes desired one; and the wiring forming step of polishing the formed copper wiring layer into a wiring.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: June 7, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Michie Sunayama, Noriyoshi Shimizu, Masaki Haneda
  • Spacer-less transistor integration scheme for high-K gate dielectrics and small gate-to-gate spaces applicable to Si, SiGe and strained silicon schemes
    Patent number: 7955919
    Abstract: A transistor integration process provides a damascene method for the formation of gate electrodes and gate dielectric layers. An interlayer-dielectric film is deposited prior to the gate electrode formation to avoid the demanding gap fill requirements presented by adjacent gates. A trench is formed in the interlayer-dielectric film followed by the deposition of the gate material in the trench. This process avoids the potential for damage to high-k gate dielectric layers caused by high thermal cycles and also reduces or eliminates the problematic formation of voids in the dielectric layers filling the gaps between adjacent gates.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: June 7, 2011
    Assignee: LSI Corporation
    Inventors: David Pritchard, Hemanshu Bhatt, David T. Price
  • Method for fabricating semiconductor device
    Patent number: 7951667
    Abstract: A method of fabricating a vertical transistor in a semiconductor device improves integration of the semiconductor device according to a design rule. After a semiconductor substrate is etched to form a buried bit line, a gate electrode pattern that surrounds a cylindrical channel region pattern of the vertical transistor is formed, thereby preventing damage to the gate electrode pattern due to an etching process. The gate electrode pattern surrounds the channel region pattern where a width is narrower than second source and drain regions. The second source and drain regions are then deposited over the channel region pattern and the gate electrode pattern. As a result, a neck-shaped channel region does not collapse due to the weight of the second source and drain regions.
    Type: Grant
    Filed: December 5, 2008
    Date of Patent: May 31, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jin Soo Kim
  • Method of fabricating semiconductor device
    Patent number: 7951654
    Abstract: A semiconductor device is fabricated by forming a first crystalline region by irradiating a laser beam to a first region of an amorphous semiconductor film by relatively moving the laser beam with respect to the first region of the amorphous semiconductor film. A second crystalline region is formed by irradiating the laser beam to a second region of the amorphous semiconductor film including a portion of the first crystalline region by relatively moving the laser beam with respect to the second region of the amorphous semiconductor film. The wavelength of the laser beam falls in a range of 370 rim through 650 nm. In general, crystalline performance of the first crystalline region, the second crystalline region, and a region of overlap between the first crystalline region and the second crystalline region are the same.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: May 31, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Koichiro Tanaka