Abstract: Many digital processors have an asynchronous bus controlled by two control signals. To interface a synchronous memory to an asynchronous bus, interface logic is required. In an interface for transferring data from an asynchronous circuit to a synchronous circuit, data to be written are written in an intermediate register while timing control signals are being synchronized to a system clock by means of flip-flops. Correspondingly, in an interface for transferring data from the synchronous circuit to the asynchronous circuit, a signal indicating a read transaction from the synchronous circuit is synchronized to the system clock by means of a flip-flop circuit.

Abstract: A digital matched filter for a CDMA radio comprises a digital delay line having a plurality of successive delay stages adapted to receive a digital signal and propagate the digital signal therethrough at a fixed rate. A correlator is coupled to the digital delay line to correlate the digital signal to a predefined spreading code to provide a correlation signal representing a degree of correlation of the digital signal to the spreading code. A window logic unit is coupled to the correlator to enable operation of the correlator only during successive discrete time periods of the correlation signal corresponding to a high degree of correlation of the digital signal to the spreading code.

Abstract: A pseudo-random noise series generator which can change the timing of generation of a PN series arbitrarily and with no instantaneous cut-off of the output. At the time of system start, the whole period or a certain beginning length of a PN series generated by a tapped shift register is stored into a RAM. The stored PN series is output from a position designated by an address signal. An address generator for generating the address signal on an externally applied timing control signal increments an address by one for each step from an initial value set by the timing control signal. In the case where a new timing different from the old timing is set by the timing control signal, the address is incremented or decremented instantaneously by a difference between the old timing and the new timing and a normal incrementing operation is thereafter started again.

Abstract: According to the present disclosure, aperiodic data is applied to parallel register (500). When a predetermined relationship between an aperiodic load signal and a periodic oversample clock signal occurs, the aperiodic data is latched to the output (506) of the parallel register as substantially periodic data. The substantially periodic data is loaded into a sigma-delta DAC (502) for processing. The sigma-delta DAC (502) is driven by a periodic oversample clock to produce a 1-bit oversampled, time averaged representation of the substantially periodic data.

Abstract: A communication control system includes a first communication control apparatus connected to one end portion of each of a clock signal line and a data signal line, and a second communication control apparatus connected to the other end portion of each of the clock signal line and the data signal line.

Abstract: An error indicator indicates plural errors with a light emitter. A MPU checks each section in a data modulator-demodulator, and flashes an error LED at a standard cycle when any error occurs. When an user turns ON an error check key in flashing at the standard cycle, the MPU varies a flashing cycle of the error LED in accordance with the detected error. Moreover, a light emitter in a data modulator-demodulator indicates whether a remote loop back test is executed by a trigger from a self-station or from other station. The MPU lights a test LED and shifts the data modulator-demodulator to an execution state when any switch is turned ON. When any of test switches except for local digital/analog loop back test is turned ON, the MPU transmits a test command corresponding to the test switch which is turned ON to other data modulator-demodulator. The other data modulator-demodulator flashes the test LED and is shifted to the execution state corresponding to the received command.

Abstract: A communication system includes a data sampling rate converter that uses a closed-loop control arrangement to convert an input signal at a first sampling rate to a second, asynchronous, sampling rate without requiring extensive input buffering. A number of data registers in a first-in-first-out input buffer are used to receive and store data samples at the first rate and to pass the data samples from the input buffer at a controlled rate. The input buffer indicates the current capacity of the input buffer circuit for use by a frequency ratio estimation circuit, which is arranged to respond by providing an estimate of the actual ratio between the first rate and the second rate. A control circuit responds to the frequency ratio estimation circuit by generating the controlled rate at which the data samples are to be passed from the input buffer. In this manner, the data samples are passed from the input buffer at the controlled rate for processing and outputting the data at the second rate.

Abstract: A multicarrier transmission system (100) routes data symbols from a data source (142) to a multicarrier modulator (145). Each modulator (201, 202, 203) within the multicarrier modulator (145) is coupled to a corresponding gain adjuster (211, 212, 213) that distributes the available transmit power across various subcarriers. Power distribution, is determined in part, upon the noise sensitivity of the transmitted information. In accordance, data stream symbols of like sensitivity are grouped (520) and transmitted during defined time intervals. Each such group is assigned a unique transmission power level (530). At any given moment in time, all subcarrier transmission power levels will have an identical amplitude, thereby mitigating the impact of subchannel-to-subchannel interference.

Abstract: A radio receiver includes a plurality of demodulating units for demodulating a received radio wave received via a plurality of paths so as to produce respective demodulated signals, and combining units for executing a combination process of synchronizing and combining the demodulated signals produced by the plurality of demodulating units, the combining units correlating the demodulated signals produced by the plurality of demodulating units and excluding from a combination process a demodulated signal that meets a predetermined condition based on a predetermined algorithm.

Abstract: A communication system (10) implemented to be specifically matched to the time and spatially dependent statistics of a transmission channel (36). The communication system (10) is used for broadcasting over the channel (36) to users in a coverage region (18). The communication system (10) includes a transmitter (12) having an error correction encoder (30) and a weighted interleaver (32). The error correction encoder (30) includes a first input to receive data bits and a first output. The error correction encoder (30) expands each data bit received at said input by an encoder rate. The weighted interleaver (32) includes a second input to receive the expanded data bits and a second output. The weighted interleaver (32) has a non-uniform delay distribution between a minimum delay and a maximum delay to interleave the expanded data bits by the non-uniform delay distribution.

Abstract: A swept frequency communication system includes a modulator that multiplies a frequency sweep signal with one or more underlying modulated communication signals to produce a swept frequency signal having a number of headerless tracks located directly adjacent one another in the swept frequency/time domain. A demodulator receives the swept frequency signal after that signal has been passed through a wireless channel, isolates a particular track of the received swept frequency signal to prevent a near/far problem, A/D converts the isolated track, resweeps the digitized isolated track, and then equalizes the isolated track using a blind channel equalizer to eliminate time-varying amplitude/phase impairments caused by transmission of that track through the wireless channel. The demodulator then removes the sweep signal from the equalized swept frequency track and decodes or demodulates the underlying modulated communication signal.

Abstract: A receiver for a spectrum spread communication system capable of eliminating a deterioration in receive quality due to fading by multipass. A signal of which a spectrum is spread by a direct spread modulation system is transmitted from a transmit side unit. A receive side unit is provided with a plurality of receive antennas, through which receive signals are fed to receiver circuits, followed by conversion of each of the signals into an intermediate frequency signal. Then, the signal is fed to a signal intensity measurement circuit and sampled by a clock n (n: an integer) times as high as a chip frequency, resulting in an intensity thereof being measured. Depending on results of the measurement, a selection signal is fed to a path switching circuit, resulting in one of outputs of the receiver circuits being selected, which is then fed to a direct spread demodulation circuit.

Abstract: A receiver including a signal reception unit, for receiving a signal from a dynamically fading channel, a demodulator, connected to the signal reception unit, for demodulating the received signal, thereby producing a demodulated signal therefrom, a quantizing processor, connected to the demodulator and to the signal reception unit, for analyzing the received signal and for quantizing the demodulated signal, thereby producing a quantized signal, and a decoder, connected to the quantzing processor, for decoding the quantized signal, wherein the quantizing processor normalizes the demodulated signal according to the estimated fading of the received signal.

Abstract: A signal processing system receives and mixes a plurality of analog input signals having a maximum frequency. Each analog input signal is connected to an input of a modulator producing a high frequency oversampled digital signal. Each high frequency oversampled signal is connected to an input of a first decimation filter which produces an intermediate frequency oversampled multiple bit signal. Each of the intermediate frequency oversampled signals is connected to a respective input of a first digital mixer which produces a single mixed multiple bit output signal. The single mixed multiple bit output signal is connected to a second decimation filter which produces a final digital output signal, at a frequency suitable for representing the mixed analog input signals.

Abstract: An apparatus for transmitting a digital information signal includes an input terminal for receiving the digital information signal, a first channel encoding unit for carrying out a first channel encoding step on an information word in a series of subsequent information words included in the digital information signal so as to obtain a channel word, a compression unit for carrying out a compression step on a channel word so as to obtain a compressed channel word, an error correction encoding unit for carrying out an error correction encoding of the compressed channel word so as to obtain a parity word, a second channel encoding unit for carrying out a second channel encoding step on the parity word so as to obtain a channel encoded parity word, and a formatting unit for combining the channel word and the channel encoded parity word into a composite transmission signal suitable for transmission via a transmission medium.

Abstract: An impulse radio communications system using one or more subcarriers to communicate information from an impulse radio transmitter to an impulse radio receiver. The impulse radio communication system is an ultrawide-band time domain system. The use of subcarriers provides impulse radio transmissions added channelization, smoothing and fidelity. Subcarriers of different frequencies or waveforms can be used to add channelization of impulse radio signals. Thus, an impulse radio link can communicate many independent channels simultaneously by employing different subcarriers for each channel. The impulse radio uses modulated subcarrier(s) for time positioning a periodic timing signal or a coded timing signal. Alternatively, the coded timing signal can be summed or mixed with the modulated subcarrier(s) and the resultant signal is used to time modulate the periodic timing signal. Direct digital modulation of data is another form of subcarrier modulation for impulse radio signals.

Abstract: A transmitter for a communication system transmits consecutive chips of a signal shifted in phase +/-90 degrees +/- nan angle between 0 degrees and 45 degrees which is a function of a spreading gain.

Abstract: An antenna receives an analog waveform and an analog signal indicative of the amplitude and frequency of the analog waveform. The analog signal is processed in a plurality of parallel digital processing channels each arranged to digitize the analog signal at a corresponding sampling frequency f.sub.si to produce a plurality of digital signals. A discrete Fourier transform is applied to each of the digital signals output to produce a corresponding plurality of unique Fourier spectra of length m.sub.i =(f.sub.si)(T.sub.Li) where T.sub.Li is the integration time for the discrete Fourier transform for each digital processing channel. The lengths of the Fourier spectra (m.sub.i) are selected to be pairwise relatively prime. The discrete Fourier transform encodes the signals in same form as the symmetrical number system (SNS). A SNS-to-decimal algorithm is then applied to the detected bin values (a.sub.i) to determine the numerical value of the frequency f of the analog waveform.

Abstract: A network interface for receiving both high speed signals and low speed signals includes a passive filter manufactured entirely from passive electronic elements. The filter filters the low speed signal when a low speed signal is received, and does not distort a high speed signal transmitted to an encoder/decoder device when a high speed signal is received.

Abstract: A method and circuitry are provided for generating a phase shift in the recovered clock in a high speed, digital data recovery phase locked loop. Since phase step injection can be done in a closed loop environment, the dynamic of the real time phase step response of the PLL can be analyzed using a phase meter. In an open-loop environment, the output of the phase meter with a step response of 60 degree phase shift tracks closely with the internal RC response at the multi-phase outputs of the PLL's phase-to-frequency converter. Since the register and capacitor values vary with process, the scheme for verifying the relative accuracy of the PLL's internal filters can be verified without actually probing the device.