Patents Examined by Michelle Estrada
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Patent number: 8013364Abstract: A structure having air gaps between interconnects is disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.Type: GrantFiled: October 15, 2009Date of Patent: September 6, 2011Assignee: Infineon Technologies AGInventors: Markus Naujok, Hermann Wendt, Alois Gutmann, Muhammed Shafi Pallachalil
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Patent number: 8008181Abstract: Misfit dislocations are redirected from the buffer/Si interface and propagated to the Si substrate due to the formation of bubbles in the substrate. The buffer layer growth process is generally a thermal process that also accomplishes annealing of the Si substrate so that bubbles of the implanted ion species are formed in the Si at an appropriate distance from the buffer/Si interface so that the bubbles will not migrate to the Si surface during annealing, but are close enough to the interface so that a strain field around the bubbles will be sensed by dislocations at the buffer/Si interface and dislocations are attracted by the strain field caused by the bubbles and move into the Si substrate instead of into the buffer epi-layer. Fabrication of improved integrated devices based on GaN and Si, such as continuous wave (CW) lasers and light emitting diodes, at reduced cost is thereby enabled.Type: GrantFiled: August 12, 2009Date of Patent: August 30, 2011Assignee: The Regents of The University of CaliforniaInventors: Zuzanna Liliental-Weber, Rogerio Luis Maltez, Hadis Morkoc, Jinqiao Xie
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Patent number: 8008123Abstract: A manufacturing method of a semiconductor device, including a first step of forming a first electrode pad at an external edge part of a semiconductor chip mounting area of a supporting board; a second step of fixing a rear surface of a semiconductor chip having a main surface, the main surface where a second electrode pad is formed, to an inside of an area of the main surface of the supporting board, the area where the first electrode pad is formed; a third step of forming a first internal connecting terminal on the first electrode pad, and forming a second internal connecting terminal on the second electrode pad; and a fourth step of forming a first insulation layer on the main surface of the supporting board.Type: GrantFiled: September 29, 2010Date of Patent: August 30, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventor: Syota Miki
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Patent number: 8003475Abstract: A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.Type: GrantFiled: March 20, 2008Date of Patent: August 23, 2011Assignee: Infineon Technologies AGInventors: Josef Böck, Rudolf Lachner, Thomas Meister, Reinhard Stengl, Herbert Schäfer, Martin Seck
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Patent number: 7998829Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material using an electrochemical etch to form a first cavity, a second cavity, wherein the first cavity is isolated from the second cavity, a first protrusion is between the first cavity and the second cavity, and the semiconductor material comprises silicon. The method further includes performing a thermal oxidation to convert a portion of the silicon of the semiconductor material to silicon dioxide and forming a first dielectric material over the first cavity, over the second cavity, over at least a portion of the semiconductor material, and over at least a portion of the first protrusion. Other embodiments are described and claimed.Type: GrantFiled: December 9, 2008Date of Patent: August 16, 2011Assignee: HVVi Semiconductors, Inc.Inventor: Michael Albert Tischler
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Patent number: 7993973Abstract: The present invention provides a structure combining an IC integrated substrate and a carrier, which comprises a carrier and an IC integrated substrate formed on the carrier. The interface between the IC integrated substrate and the carrier has a specific area at which the interface adhesion is different from that at the remaining area of the interface. The present invention also provides a method of manufacturing the above structure and a method of manufacturing electronic devices using the above structure.Type: GrantFiled: November 7, 2008Date of Patent: August 9, 2011Assignee: Princo Corp.Inventor: Chih-kuang Yang
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Semiconductor substrate, semiconductor device, and method for manufacturing the semiconductor device
Patent number: 7994574Abstract: A double-structure silicon on insulator (SOI) substrate with a silicon layer, an insulation film (silicon oxide film), a silicon layer, and an insulation film in this order from the side of the surface. The upper-layer insulation film is formed so as to have a uniform distribution of depth while the lower-layer insulation film is formed so as to have a non-uniform distribution of depth so that a thick portion may be formed in the silicon layer along a predetermined path. The refractive index of Si is 3.5 and the refractive index of SiO2 is 1.5. The thick portion of the silicon layer provides a core and the insulation films corresponding to this thick portion provide clads, thereby forming an optical waveguide along the predetermined path. The silicon layer at the side of the surface has a uniform thickness, thereby enabling characteristics of MOS devices fabricated on various portions of the silicon layer to be met with each other easily and facilitating a design of the electrical device as a whole.Type: GrantFiled: November 17, 2006Date of Patent: August 9, 2011Assignee: Sony CorporationInventor: Koichiro Kishima -
Patent number: 7993970Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The method is carried out by forming solder pads on a substrate by wet etching, flipping a semiconductor chip having a plurality of connection bumps formed on an active surface of the semiconductor chip for the connection bumps to be mounted by compression on the solder pads of the substrate correspondingly, at a temperature of the compression between the connection bumps and the solder pads lower than the melting points of the solder pads and the connection bumps, so as to allow the semiconductor chip to be engaged with and electrically connected to the substrate through the connection bumps and the solder pads, thereby enhancing the bonding strength of the solder pads and the connection bumps and increasing the fabrication reliability.Type: GrantFiled: March 27, 2009Date of Patent: August 9, 2011Assignee: UTAC (Taiwan) CorporationInventor: Shiann-Tsong Tsai
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Patent number: 7994040Abstract: A method for forming a semiconductor device is disclosed. A substrate including a gate dielectric layer and a gate electrode layer sequentially formed thereon is provided. An offset spacer is formed on sidewalls of the gate dielectric layer and the gate electrode layer. A carbon spacer is formed on a sidewall of the offset spacer, and the carbon spacer is then removed. The substrate is implanted to form a lightly doped region using the gate electrode layer and the offset spacer as a mask. The method may also include providing a substrate having a gate dielectric layer and a gate electrode layer sequentially formed thereon. A liner layer is formed on sidewalls of the gate electrode layer and on the substrate. A carbon spacer is formed on a portion of the liner layer adjacent the sidewall of the gate electrode layer. A main spacer is formed on a sidewall of the carbon spacer. The carbon spacer is removed to form an opening between the liner layer and the main spacer.Type: GrantFiled: April 13, 2007Date of Patent: August 9, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Min-Hwa Chi, Wen-Chuan Chiang, Mu-Chi Chiang, Chang-Ku Chen
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Patent number: 7981706Abstract: A photoresist composition includes an alkali-soluble resin, a dissolution inhibitor including a quinone diazide compound, a first additive including a benzenol compound represented by the following Chemical Formula 1, a second additive including an acrylic copolymer represented by the following Chemical Formula 2 and an organic solvent. Accordingly, heat resistance of a photoresist pattern may be improved, and the photoresist pattern may be readily stripped. As a result, crack formation in the photoresist pattern may be reduced and/or prevented.Type: GrantFiled: September 28, 2010Date of Patent: July 19, 2011Assignees: Samsung Electronics Co., Ltd., Dongwoo Fine-ChemInventors: Jeong-Min Park, Jung-Soo Lee, Won-Young Chang, Eun-Sang Lee, In-Ho Yu, Seong-Hyeon Kim
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Patent number: 7982296Abstract: The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.Type: GrantFiled: September 22, 2009Date of Patent: July 19, 2011Assignee: The Board of Trustees of the University of IllinoisInventors: Ralph G. Nuzzo, John A. Rogers, Etienne Menard, Keon Jae Lee, Dahl-Young Khang, Yugang Sun, Matthew Meitl, Zhengtao Zhu
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Patent number: 7982310Abstract: A semiconductor device is provided comprising: a semiconductor element including a plurality of electrodes; first wirings coupled to the electrodes and directed toward a center of the semiconductor element from a portion coupled to the electrodes; second wirings coupled between the first wirings and external terminals, the second wirings being directed to an outer area of the semiconductor element relative to the center; and at least one resin layer formed between the first wirings and the second wirings.Type: GrantFiled: September 29, 2009Date of Patent: July 19, 2011Assignee: Seiko Epson CorporationInventor: Haruki Ito
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Patent number: 7980198Abstract: It is an object of the present invention to provide a doping apparatus, a doping method, and a method for fabricating a thin film transistor that can carry out doping to the carrier concentration which is optimum for obtaining the desired electric characteristic non-destructively and in an easy manner. In accordance with the present invention, an electric characteristic of a semiconductor element (threshold voltage in a transistor and the like) is correctly and precisely monitored by using a contact angle, and is controlled by controlling a doping method. In addition, the present invention can be momentarily acquired information by in-situ monitoring the characteristic and can be fed back without a time lag.Type: GrantFiled: April 7, 2010Date of Patent: July 19, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Junichi Koezuka, Naoto Yamade
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Patent number: 7968421Abstract: Manufacturing a semiconductor device includes defining bulb-type trenches having spherical portions in a silicon substrate. Oxide layers are formed in surfaces of spherical portions of the bulb-type trenches by conducting an oxidation process for the silicon substrate having the bulb-type trenches defined therein. An insulation layer is formed on the entire surface of the silicon substrate including the surfaces of the bulb-type trenches, which have the oxide layers formed in the surfaces of the spherical portions thereof. Isolation trenches are defined by etching the insulation layer, whereby SOI structures having the oxide layers interposed between portions of the silicon substrate are formed.Type: GrantFiled: December 11, 2008Date of Patent: June 28, 2011Assignee: Hynix Semiconductor Inc.Inventor: Min Jung Shin
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Patent number: 7968436Abstract: Copper diffusion barrier films having low dielectric constants are suitable for a variety of copper/inter-metal dielectric integration schemes. Copper diffusion barrier films in accordance with the invention are composed of one or more layers of silicon carbide, at least one of the silicon carbide layers having a composition of at least 40% carbon (C), for example, between about 45 and 60% carbon (C). The films' high carbon-content layer will have a composition wherein the ratio of C to Si is greater than 2:1; or >3:1; or >4:1; or >5.1. The high carbon-content copper diffusion barrier films have a reduced effective k relative to conventional barrier materials.Type: GrantFiled: July 2, 2009Date of Patent: June 28, 2011Assignee: Novellus Systems, Inc.Inventors: Yongsik Yu, Karen Billington, Xingyuan Tang, Haiying Fu, Michael Carris, William Crew
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Patent number: 7968474Abstract: The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e.g., an alternating current electric field) is used to align and associate nanowires with electrodes. By modulating the energizing, the nanowires are coupled to the electrodes such that they remain in place during subsequent wash and drying steps. The invention also provides methods for transferring nanowires from one substrate to another in order to prepare various device substrates. The present invention also provides methods for monitoring and controlling the number of nanowires deposited at a particular electrode pair, as well as methods for manipulating nanowires in solution.Type: GrantFiled: November 9, 2007Date of Patent: June 28, 2011Assignees: Nanosys, Inc., Sharp Kabushiki KaishaInventors: Samuel Martin, Xiangfeng Duan, Katsumasa Fujii, James M. Hamilton, Hiroshi Iwata, Francisco Leon, Jeffrey Miller, Tetsu Negishi, Hiroshi Ohki, J. Wallace Parce, Cheri X. Y. Pereira, Paul John Schuele, Akihide Shibata, David P. Stumbo, Yasunobu Okada
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Patent number: 7964459Abstract: A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns.Type: GrantFiled: December 10, 2009Date of Patent: June 21, 2011Assignee: Spansion Israel Ltd.Inventors: Eli Lusky, Assaf Shappir, Rustom Irani, Boaz Eitan
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Patent number: 7964038Abstract: Methods and apparatus for providing an improved azimuthal thermal uniformity of a substrate are provided herein. In some embodiments, a substrate support for use in a semiconductor process chamber includes a susceptor plate; and a supporting member to support a backside of the susceptor plate proximate an outer edge thereof, wherein the supporting member substantially covers the backside of the susceptor plate. In some embodiments, the substrate support is disposed in a process chamber having at least some lamps disposed below the supporting member and utilized for heating the back side of the susceptor plate.Type: GrantFiled: October 2, 2008Date of Patent: June 21, 2011Assignee: Applied Materials, Inc.Inventors: Kailash Kiran Patalay, Jean R. Vatus, Dean Berlin
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Patent number: 7960256Abstract: In a first aspect, a method of forming an epitaxial film on a substrate is provided. The method includes (a) providing a substrate; (b) exposing the substrate to a silicon source and a carbon source so as to form a carbon-containing silicon epitaxial film; (c) encapsulating the carbon-containing silicon epitaxial film with an encapsulating film; and (d) exposing the substrate to Cl2 so as to etch the encapsulating film. Numerous other aspects are provided.Type: GrantFiled: May 12, 2010Date of Patent: June 14, 2011Assignee: Applied Materials, Inc.Inventors: Zhiyuan Ye, Yihwan Kim, Xiaowei Li, Ali Zojaji, Nicholas C. Dalida, Jinsong Tang, Xiao Chen, Arkadii V. Samoilov
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Patent number: 7960806Abstract: A sub-mount, a light emitting diode package, and a method of manufacturing thereof are disclosed. A sub-mount, on which multiple light emitting diodes are mounted, can include a multiple number of metal bodies on which the light emitting diodes are respectively mounted, and an oxide wall interposed between the metal bodies such that the adjacent metal bodies are supported by each other but electrically disconnected from each other. By utilizing certain embodiments of the invention, a high heat releasing effect may be obtained, and manufacturing costs may be reduced.Type: GrantFiled: October 1, 2008Date of Patent: June 14, 2011Assignee: Samsung LED Co., Ltd.Inventors: Young-Ki Lee, Seog-Moon Choi, Hyung-Jin Jeon, Sang-Hyun Shin