Abstract: It is an object of the present invention to provide a doping apparatus, a doping method, and a method for fabricating a thin film transistor that can carry out doping to the carrier concentration which is optimum for obtaining the desired electric characteristic non-destructively and in an easy manner. In accordance with the present invention, an electric characteristic of a semiconductor element (threshold voltage in a transistor and the like) is correctly and precisely monitored by using a contact angle, and is controlled by controlling a doping method. In addition, the present invention can be momentarily acquired information by in-situ monitoring the characteristic and can be fed back without a time lag.

Abstract: A method for forming a bit-line contact plug includes providing a substrate including a transistor which includes a gate structure and a source/drain at both sides of the gate structure; forming a conductive layer, a bit-line contact material layer and a hard mask layer; performing an etching process using the conductive layer as an etching stop layer to etch the bit-line contact material layer and the hard mask layer and forming the bit-line contact plug on the source/drain. A transistor structure includes a gate structure and a source/drain at both sides of the gate structure, a conductive layer covering part of the gate structure and connected to the source/drain, and a bit-line contact plug disposed on the conductive layer and directly connected to the conductive layer.

Abstract: A method of forming a crystalline silicon layer on a microrough face of a substrate by reducing the microroughness of the face and then performing a metal induced crystallization process on the face is disclosed. The method further comprises, after metal induced crystallization and before removing the metal layer, removing silicon islands using the metal layer as a mask.

Abstract: An integrated circuit (IC) includes a high voltage first-conductivity type field effect transistor (HV-first-conductivity FET) and a high voltage second-type field effect transistor (HV-second-conductivity FET). The HV first-conductivity FET has a second-conductivity-well and a field oxide formed over the second-conductivity-well to define an active area. A first-conductivity-well is formed in at least a portion of the active area, wherein the first-conductivity-well is formed to have the capability to operate as a first-conductivity-drift portion of the HV-first-conductivity FET. The HV second-conductivity FET has a first-conductivity-well and a field oxide formed over the first-conductivity-well to define an active area. A channel stop region I s formed in at least a portion of the active area, wherein the channel stop region is formed to have the capability to operate as second-conductivity? drift portions of the HV-second-conductivity FET.

Abstract: A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.

Abstract: A housing accommodating a semiconductor chip is set out. The housing and chip may be used for sending and/or receiving radiation. Popular applications of the housing may be in light emitting diodes. The housing includes a conductor strip that is punched into two electrically isolated portions. The housing further includes a cavity extending inwards from the top of the housing. The conductor portions include respective areas that are exposed at the bottom of the cavity. The semiconductor chip is bonded to one of the exposed areas and a wire bonds the chip to the second exposed area. The conductor portions also terminate in exposed electrodes, which allow for electrical connection of the chip with external devices. A window is formed in the cavity and the walls of the housing that form the cavity may be made of a reflective material. The electrodes remain unexposed to the window but for any residual areas about the chip and bonding wire within the first and second exposed areas.

Abstract: A reliable semiconductor device including support bumps so as to adequately seal the region between the chips is to be provided. The semiconductor device includes a semiconductor chip; a bump formed on an upper face of the semiconductor chip; and a plurality of support bumps formed along a circumference of the region where the bump is provided, formed on the upper face of the semiconductor chip; and a flow path for a sealing resin is provided between the plurality of support bumps, so as to connect the region where the bump is provided and a periphery region of the semiconductor chip.

Abstract: Disclosed are a flash memory device having a silicon-oxide-nitride-oxide-silicon (SONOS) structure and a method of manufacturing the same. The flash memory device includes source and drain diffusion regions separated from each other on opposite sides of a trench in an active region of a semiconductor substrate, a control gate inside the trench and protruding upward from the substrate, a charge storage layer between the control gate and an inner wall of the trench, and a pair of insulating spacers formed on opposite sidewalls of the control gate with the charge storage layer therebetween. Here, the charge storage layer has an oxide-nitride-oxide (ONO) structure. Further, the depth of the trench from the surface of the substrate is greater than that of each of the source and drain diffusion regions.

Abstract: Disclosed is a method for fabricating a transistor of a memory device capable of preventing voids from being created when forming a low-resistant gate electrode. The method includes the steps of forming an active area by etching a semiconductor substrate, forming a field oxide layer in the semiconductor substrate and forming a recess by etching the field oxide layer. A gate insulation layer is formed along an upper surface of the active area and an exposed portion of the active area. A gate electrode is formed on the field oxide layer such that the gate electrode extends across an upper portion of the active area while being overlapped with a channel area and the recess. The first conductive layer to be patterned has the same thickness, so the low-resistant gate electrode is easily fabricated without forming the voids.

Abstract: Methods for fabricating a FinFET structure are provided. One method comprises forming a hard mask layer on a gate-forming material layer having a first portion and a second portion. A plurality of mandrels are fabricated on the hard mask layer and overlying the first portion and the second portion of the gate-forming material layer. A sidewall spacer material layer is deposited overlying the plurality of mandrels. The sidewall spacer material layer overlying the first portion of the gate-forming material layer is partially etched. Sidewall spacers are fabricated from the sidewall spacer material layer, the sidewall spacers being adjacent sidewalls of the plurality of mandrels. The plurality of mandrels are removed, the hard mask layer is etched using the sidewall spacers as an etch mask, and the gate-forming material layer is etched using the etched hard mask layer as an etch mask.

Abstract: In a first aspect, a first method of forming an epitaxial film on a substrate is provided. The first method includes (a) providing a substrate; (b) exposing the substrate to at least a silicon source so as to form an epitaxial film on at least a portion of the substrate; and (c) exposing the substrate to HCl and Cl2 so as to etch the epitaxial film and any other films formed during step (b). Numerous other aspects are provided.

Abstract: A method of making a semiconductor device includes providing a first wafer and providing a second wafer having a first side and a second side, the second wafer including a semiconductor substrate, a storage layer, and a layer of gate material. The storage layer may be located between the semiconductor structure and the layer of the gate material and the storage layer may be located closer to the first side of the second wafer than the semiconductor structure. The method further includes boding the first side of the second wafer to the first wafer. The method further includes removing a first portion of the semiconductor structure to leave a layer of the semiconductor structure after the bonding. The method further includes forming a transistor having a channel region, wherein at least a portion of the channel region is formed from the layer of the semiconductor structure.

Abstract: A method for manufacturing a vertical MOS transistor comprising forming a protrusion-like region, forming a silicon oxide film on an exposed surface of the protrusion-like region and a surface of the silicon semiconductor substrate, increasing a film thickness of at least the silicon oxide film on the silicon semiconductor substrate by thermal oxidation to form a first insulating film, forming a lower impurity diffusion region, removing the silicon oxide film to expose a silicon side of the protrusion-like region, thermally oxidizing the silicon side to form a second insulating film having a thinner film thickness than a film thickness of the first insulating film, forming a gate electrode over a side of the protrusion-like region, and forming an upper impurity diffusion region.

Abstract: A method of manufacturing a thin-film semiconductor device, including forming a crystallized region on a transparent insulating substrate, implanting an impurity into the crystallized region and an amorphous semiconductor layer to form a source diffusion region and a drain diffusion region in the crystallized region, subjecting the resultant structure to heat treatment, thereby not only activating the impurity implanted in the crystallized region and the amorphous semiconductor layer but also restoring crystallinity of only a portion of the amorphous semiconductor layer which is formed on the crystallized region to thereby turn the portion into a polycrystalline semiconductor layer, and subjecting the resultant surface to selective etching to thereby leave only the polycrystalline semiconductor layer and to remove the amorphous semiconductor layer formed on other regions, thereby forming, in a self-aligned manner, a stacked source diffusion layer and a stacked drain diffusion layer.

Abstract: An LED has a light-generating semiconductor region formed on a baseplate via a metal-made reflector layer. The light-generating semiconductor region has an active layer sandwiched between a pair of claddings of opposite conductivity types. An annular marginal space is left around the reflector layer between the light-generating semiconductor region and the substrate. In order to preclude the thermal migration of the reflector metal onto the side surfaces of the light-generating semiconductor region, with a possible short-circuiting of the pair of claddings across the active layer, an anti-migration seal is received in the annular marginal space created around the reflector layer between the light-generating semiconductor region and the baseplate.

Abstract: There is provided a high voltage gate driver integrated circuit. The high voltage gate driver integrated circuit includes: a high voltage region; a junction termination region surrounding the high voltage region; a low voltage region surrounding the junction termination region; a level shift transistor disposed between the high voltage region and the low voltage region, at least some portions of the level shift transistor being overlapped with the junction termination region; and/or a high voltage junction capacitor disposed between the high voltage region and the low voltage region, at least some portions of the high voltage junction capacitor being overlapped with the junction termination region.

Abstract: An on-chip bypass capacitor and method of manufacturing the same, the on-chip bypass capacitor including at least two capacitor arrays, each capacitor array including a first layer connecting the at least two capacitor arrays in series, each capacitor array including a plurality of capacitors, each of the plurality of capacitors including a second layer connecting the plurality of capacitors in parallel. The on-chip bypass capacitor may be part of a chip which also includes a memory cell array including at least one cell capacitor.

Abstract: There is a method of forming a contact post and surrounding isolation trench in a semiconductor-on-insulator (SOI) substrate. The method comprises etching a contact hole and surrounding isolation trench from an active layer of the substrate to the insulating layer, masking the trench and further etching the contact hole to the base substrate layer, filling the trench and contact hole with undoped intrinsic polysilicon and then performing a doping process in respect of the polysilicon material filling the contact hole so as to form in situ a highly doped contact post, while the material filling the isolation trench remains non-conductive. The isolation trench and contact post are formed substantially simultaneously so as to avoid undue interference with the device fabrication process.

Abstract: Disclosed is a method involving repeatedly measuring a pressure within a flow of processing gas that is provided in a semiconductor processing apparatus for treatment of a semiconductor substrate, such as a semiconductor wafer. The flow of processing gas is made to extend between a surface of the substrate and a surface of a processing body. From the pressure measurements the occurrence of an event that is related to a variation in the position of the substrate's surface relative to the surface of the processing body is determined.

Abstract: Methods and systems are provided for LED modules that include an LED die integrated in an LED package with a submount that includes an electronic component for controlling the light emitted by the LED die. The electronic component integrated in the submount may include drive hardware, a network interface, memory, a processor, a switch-mode power supply, a power facility, or another type of electronic component.